Details:

Link up failure can occur if downstream port (Root Complex) is required to perform automatic lane reversal.

Usually, upstream port (Endpoint or Switch) detects lane reversal first and automatically performs the reversal. However, upstream port may not support lane reversal since it is optional. In this case, PCIE subsystem performs the following sequence:

1. Downstream port transitions from Configuration.Lanenum.Wait to Configuration.Lanenum.Accept state after 1ms and other conditions for this transition are met.
2. Downstream port performs lane reversal in Configuration.Lanenum.Accept state and waits for 1ms before transitioning to Configuration.Complete state.

This 1ms wait violates PCIe specification requirement, which requires downstream port to transition to Configuration.Complete immediately. In the meantime, upstream port’s 2ms timeout in Configuration.Lanenum.Wait state may have elapsed and it may have transitioned to Detect state. If this occurs, link up does not succeed and downstream port also returns back to Detect state.

There is a possibility that upstream port adds timeout margin (instead of waiting for 2ms, it may wait for 2048us). This issue does not cause link up failure if such a margin is present in upstream port.

Workaround(s):

Lane reversal can be manually performed by setting TX_LANE_FLIP_EN=1 and RX_LANE_FLIP_EN=1 in PCIE_RC_CMD_STATUS register. This has to be done during initialization, before link training is enabled by setting LTSSM_EN bit in PCIE_RC_CMD_STATUS register.

This requires system level mechanism for software to be notified if lane reversal is required. There are four possibilities to consider:

1. Lanes are not reversed in both RC and EP/switch board designs.
2. Lanes are reversed in RC board design and not reversed in EP/switch board design.
3. Lanes are not reversed in RC board design and reversed in EP/switch board design.
4. Lanes are reversed in both RC and EP/switch board designs.

If it is known whether lanes are reversed at both RC and EP/switch sides, then software can perform lane reversal manually if it is case 2 or case 3.

If it is only known whether RC board has lanes reversed, then software may perform lane reversal considering only the RC side. However, cases 3 and 4 will not be covered by this approach. Since EP/switch board is reversing lanes, it is likely that EP/switch automatically corrects for lane reversal at its end.

There is no workaround for the case where all of the below are true:

• EP/Switch may reverse its lanes.
• There is no method for informing RC software whether EP/Switch has reversed lanes.
• EP/Switch does not support automatic lane reversal in its LTSSM and it does not manually correct lane reversal done by its board.