SPRZ171T December   2004  – September 2020 SM320F2801-EP , SM320F2808-EP , TMS320F2801 , TMS320F2801-Q1 , TMS320F28015 , TMS320F28016 , TMS320F28016-Q1 , TMS320F2802 , TMS320F2802-Q1 , TMS320F2806 , TMS320F2806-Q1 , TMS320F2808 , TMS320F2808-Q1 , TMS320F2809 , TMS320F2809-Q1

 

  1. 1Introduction
  2. 2Device and Development Tool Support Nomenclature
  3. 3Device Markings
  4. 4Silicon Change Overview
  5. 5Usage Notes and Known Design Exceptions to Functional Specifications
    1. 5.1 Usage Notes
      1. 5.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
    2. 5.2 Known Design Exceptions to Functional Specifications
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
  6. 6Documentation Support
  7. 7Trademarks
  8. 8Revision History

Advisory

ADC: ADC Inaccuracy at Low Frequencies

Revision(s) Affected

0, A on F2809 silicon

0, A on C280x silicon

0, A, B, C on F2801, F2802, F2806, F2808, and F2801x silicon

Details

At ADCCLK frequencies of less than 1 MHz, the ADC may give inaccurate results on some devices. The inaccuracy will be worse at cold temperature. Small ACQPS settings (less than 3) are more likely to show the inaccuracy.

Workaround(s)

Operate ADCCLK at 1 MHz or above.

There is no performance improvement gained by operating the ADCCLK at low frequencies. It is recommended that ADCCLK be set at the maximum value specified in the data sheet or down to one-half the maximum value specified in the data sheet.