SPRZ171T December   2004  – September 2020 SM320F2801-EP , SM320F2808-EP , TMS320F2801 , TMS320F2801-Q1 , TMS320F28015 , TMS320F28016 , TMS320F28016-Q1 , TMS320F2802 , TMS320F2802-Q1 , TMS320F2806 , TMS320F2806-Q1 , TMS320F2808 , TMS320F2808-Q1 , TMS320F2809 , TMS320F2809-Q1

 

  1. 1Introduction
  2. 2Device and Development Tool Support Nomenclature
  3. 3Device Markings
  4. 4Silicon Change Overview
  5. 5Usage Notes and Known Design Exceptions to Functional Specifications
    1. 5.1 Usage Notes
      1. 5.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
    2. 5.2 Known Design Exceptions to Functional Specifications
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
  6. 6Documentation Support
  7. 7Trademarks
  8. 8Revision History

Advisory

GPIO: Pin Behavior at Power-up

Revision(s) Affected

0, A on F2808, F2806, and F2801 silicon

Details

GPIO0-13, GPIO20-GPIO21, and GPIO25-31 can potentially drive a signal out while the device VDD and VDDIO pins are powering up, prior to the DSP receiving the first valid input clock from the X1 or XCLKIN pin. Once VDD and VDDIO are fully powered and the first clock pulse is received, the device will place these pins into a high impedance state.

Workaround(s)

None. The synchronous nature of these pins has been removed in the B revision of the silicon.