SPRZ171T December   2004  – September 2020 SM320F2801-EP , SM320F2808-EP , TMS320F2801 , TMS320F2801-Q1 , TMS320F28015 , TMS320F28016 , TMS320F28016-Q1 , TMS320F2802 , TMS320F2802-Q1 , TMS320F2806 , TMS320F2806-Q1 , TMS320F2808 , TMS320F2808-Q1 , TMS320F2809 , TMS320F2809-Q1

 

  1. 1Introduction
  2. 2Device and Development Tool Support Nomenclature
  3. 3Device Markings
  4. 4Silicon Change Overview
  5. 5Usage Notes and Known Design Exceptions to Functional Specifications
    1. 5.1 Usage Notes
      1. 5.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
    2. 5.2 Known Design Exceptions to Functional Specifications
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
  6. 6Documentation Support
  7. 7Trademarks
  8. 8Revision History

Advisory

ADC: ADC A Channel to B Channel Crosstalk in Simultaneous Mode

Revision(s) Affected

0 on TMS320C280x silicon

0, A, B on F2801, F2802, F2806, F2808, and F2801x silicon

Details

When the ADC is used in simultaneous mode, voltage present on an A channel will impact the conversion value of the associated B channel. The A channel is unaffected by the B channel.

For example, if A4/B4 are being sampled simultaneously, the converted value of B4 will have a dc error associated with the value present on A4. Voltages on the other A channels have no impact on B4; likewise, A0 affects only B0, A1 affects only B1, and so forth.

The effect of An on Bn is deterministic; from 0 to 16 codes of artificial dc increase. For example, if A channel is at 0 V, the converted B channel value will be unaffected. If An is at 1.5 V, then the Bn converted value will read 8 counts too high.

Workaround(s)

Due to the deterministic nature of the coupling from An to Bn, a simple subtraction can be made from the B channel based on the A channel result.

Formula given as:

BnC = BnM – (An /256)

BnC = Corrected result for Bn channel

BnM = Measured result for Bn channel.

Since the effect of A on B is a pure dc adder, there is no impact to linearity of the B channel. Gain and offset errors are only nominally impacted, ± 2 LSBs.

Revision C silicon has a design change to address this errata. The crosstalk will be within the datasheet specification of channel-to-channel offset. See the most recent version of the TMS320F280x, TMS320C280x, TMS320F2801x DIgital Signal Processors Data Manual for more information.