SPRUJ74 January   2023

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 EMC, EMI, and ESD Compliance
  3. 2QP-ENET Board Identification and Installation
    1. 2.1 QP-ENET Board Component Identification
    2. 2.2 Interfacing QP-ENET Expansion Board with J784S4XG01EVM Board
      1. 2.2.1 Detailed Board Assembly Procedure (J784S4XG01EVM)
  4. 3QP-ENET Expansion Board Hardware Architecture
    1. 3.1 QP-ENET Expansion Board Hardware Top Level Diagram
    2. 3.2 Expansion Connectors
    3. 3.3 Board ID EEPROM
    4. 3.4 Ethernet Interface
      1. 3.4.1 Quad Port SGMII PHY Default Configuration
      2. 3.4.2 SGMII Clocking Scheme
        1. 3.4.2.1 Main Clock
        2. 3.4.2.2 Optional Clock
      3. 3.4.3 Ethernet Port LED Indication
      4. 3.4.4 Reset and Power-down Signals
  5. 4Revision History
  6.   A Appendix
    1.     A.1 Appendix – I (Interface Mapping)
    2.     A.2 Appendix – II (QP-ENET Board GPIO Mapping)

3.4.1 Quad Port SGMII PHY Default Configuration

The QP-ENET uses the PHY of the 138-pin QFN package, designated with the XMK suffix, which supports only the SGMII interface.

The VC8514 device includes three external PHY address pins, PHYADD [4:2] to allow control of multiple PHY devices on a system board sharing a common management bus. These pins set the most significant bits of the PHY address port map. The lower two bits of the address for each port are derived from the physical address of the port (0 to 3) and the setting of the PHY address reversal bit in register 20E1, bit 9.

Table 3-3 RGMII PHY Strap Configuration
Ports SGMII Port1 SGMII Port2 SGMII Port3 SGMII Port4
Connectors J1A J1B J2A J2B
PHY Address 10010 10011 10000 10001
Auto Negotiation Enabled Enabled Enabled Enabled
ANEGSel 10/100/1000 10/100/1000 10/100/1000 10/100/1000
CLK_SQUELCH No RCVRD Clock No RCVRD Clock No RCVRD Clock No RCVRD Clock