SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Figure 9-2 shows the memory map of the BGCRC module. M0, M1, MSGRAM, LS[x]RAM, and GS[x]RAM are all zero wait-state memories. BGCRC accesses these memories with minimal impact on normal program operation. For instance, if a BGCRC access is being made to a zero wait-state memory in the current cycle, the earliest the operating program can make access to the same memory location is in the next cycle. Similarly for the non-zero wait state memories SECROM, DATAROM and BOOTROM, the worst case delay for functional access after a BGCRC access is the wait-state amount.