SPRUIU8B August   2020  – March 2026 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

  1.   1
  2.   Live Firmware Update With Device Reset on C2000 MCUs
  3.   Trademarks
  4. 1Introduction
  5. 2Resources Required for LFU
  6. 3Memory Layout
  7. 4Static Code in LFU
  8. 5LED Example Application and LFU Flow
  9. 6Running the LED Example
    1. 6.1 Serial Flash Programmer Update
    2. 6.2 Programming Static Code – Loading via Code Composer Studio (CCS)
    3. 6.3 Live Firmware Update of Application
    4. 6.4 Limitations and Troubleshooting
  10. 7Extended Implementations
    1. 7.1 Live Firmware Update with Reset on F28P65x MCUs
      1. 7.1.1 F28P65x LFU Hardware Requirements
      2. 7.1.2 Flash Organization
      3. 7.1.3 FWU Boot Mode
      4. 7.1.4 LED Example Application
        1. 7.1.4.1 LFU Command Processing
      5. 7.1.5 Running the Example
        1. 7.1.5.1 Loading the Example
        2. 7.1.5.2 Combing CPU1 and CPU2 Firmware Images
        3. 7.1.5.3 LFU over MCAN Host Programmer
          1. 7.1.5.3.1 Compiling the Host Programmer
          2. 7.1.5.3.2 Using the Host Programmer
      6. 7.1.6 Restrictions
  11. 8Revision History

7.1.2 Flash Organization

In this example, CPU1 (+ CLA) and CPU2 are each allocated two flash banks for use:

  • CPU1 + CLA (Application): Flash Banks 2 and 3
  • CPU2 (LFU): Flash Banks 0 and 1

There is an "Active" and "Inactive" flash bank per core, which specify the latest firmware to execute on reset. When an LFU occurs, CPU2 programs the inactive flash bank for CPU1 and/or CPU2, updating the flash bank's metadata to indicate the latest firmware version for FWU boot mode (provided by the Boot ROM) to decode on reset (see Section 7.1.3 for more information).

CPU1 uses the FWU boot mode to branch to the active flash bank. Then, the CPU1 application allocates the MCAN peripheral, CPU1 inactive flash, and CPU2 active/inactive flash banks to CPU2 before bringing CPU2 out of reset, booting CPU2 with FWU boot mode. After these steps are completed, CPU2 can perform an LFU as requested by the host over MCAN.

Note: CPU2 is also allocated CPU1's inactive flash bank to allow CPU2 to perform LFU for CPU1.

The LFU architecture is shown in Figure 7-2.


F28P65x LFU Architecture
Figure 7-2 F28P65x LFU Architecture