SPRUIU8B August 2020 – March 2026 TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1
CPU1 and CPU2 are both booted with the Firmware Update (FWU) boot mode. This requires that a firmware validity key (0x5A5A5A5A) and a 32-bit version number be placed at offsets 0xA and 0xC, respectively, from the application’s entry point. The flash entry points for CPU1 and CPU2 will be organized as detailed in Table 7-1.
FWU boot supports additional boot options with distinct entry points. This example leverages the various FWU boot options to ensure that CPU1 and CPU2 application versions can be distinguished by the Boot ROM. Thus, CPU1 won't mistakenly branch to a CPU2 flash bank and CPU2 won't branch to a CPU1 flash bank.
For more details on FWU boot mode, please refer to the F28P65x Technical Reference Manual's Firmware Update (FWU) Flash Boot section.
| Image Address Offset | Content |
|---|---|
| 0x0 | Application entry point (32-bit) |
| 0xA | Key (32-bit), Valid Key = 0x5A5A5A5A |
| 0xC | Firmware version number (32-bit) |