SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
The SEC inputs can be selected from various signals from in the system to enable debug and system analysis. Figure 11-3 shows the SEC inputs. Each event selector MUX can select from various signals on in the system. These signals are shown in Table 11-1.
CTM_INP_SEL, STA_INP_SEL, STO_INP_SEL, RST_INP_SEL | Input Signal | Synchronization Requirement | Polarity |
---|---|---|---|
0 | EBC1 | Disable | High |
1 | EBC2 | Disable | High |
2 | EBC3 | Disable | High |
3 | EBC4 | Disable | High |
4 | EBC5 | Disable | High |
5 | EBC6 | Disable | High |
6 | EBC7 | Disable | High |
7 | EBC8 | Disable | High |
8 | COUNTER1_EVENT | Disable | High |
9 | COUNTER2_EVENT | Disable | High |
10 | COUNTER3_EVENT | Disable | High |
11 | COUNTER4_EVENT | Disable | High |
12 | ERAD_OR_MASK0 | Disable | High |
13 | ERAD_OR_MASK1 | Disable | High |
14 | ERAD_OR_MASK2 | Disable | High |
15 | ERAD_OR_MASK3 | Disable | High |
16 | ERAD_AND_MASK0 | Disable | High |
17 | ERAD_AND_MASK1 | Disable | High |
18 | ERAD_AND_MASK2 | Disable | High |
19 | ERAD_AND_MASK3 | Disable | High |
20 | PIE_INT1 | Disable | High |
21 | PIE_INT2 | Disable | High |
22 | PIE_INT3 | Disable | High |
23 | PIE_INT4 | Disable | High |
24 | PIE_INT5 | Disable | High |
25 | PIE_INT6 | Disable | High |
26 | PIE_INT7 | Disable | High |
27 | PIE_INT8 | Disable | High |
28 | PIE_INT9 | Disable | High |
29 | PIE_INT10 | Disable | High |
30 | PIE_INT11 | Disable | High |
31 | PIE_INT12 | Disable | High |
32 | CPU_TINT0 | Disable | High |
33 | CPU_TINT1 | Disable | High |
34 | CPU_TINT2 | Disable | High |
35 | DMA_CH1INT | Disable | High |
36 | DMA_CH2INT | Disable | High |
37 | DMA_CH3INT | Disable | High |
38 | DMA_CH4INT | Disable | High |
39 | DMA_CH5INT | Disable | High |
40 | DMA_CH6INT | Disable | High |
41 | FSIRXA_DATA_PKT_RCVD | Disable | High |
42 | FSIRXA_ERROR_PKT_RCVD | Disable | High |
43 | FSIRXA_PING_PKT_RCVD | Disable | High |
44 | FSIRXA_PING_TAG_MATCH | Disable | High |
45 | FSIRXA_DATA_TAG_MATCH | Disable | High |
46 | FSIRXA_ERROR_TAG_MATCH | Disable | High |
47 | FSIRXA_FRAME_DONE | Disable | High |
48 | ADCA_EVT_INT | Disable | High |
49 | ADCB_EVT_INT | Disable | High |
50-52 | Reserved | ||
53 | ADCSOCA | Disable | High |
54 | ADCSOCB | Disable | High |
55-62 | Reserved | ||
63 | EPWMXBAR1 | Enable | Low |
64 | EPWMXBAR2 | Enable | Low |
65 | EPWMXBAR3 | Enable | Low |
66 | EPWMXBAR4 | Enable | Low |
67 | EPWMXBAR5 | Enable | Low |
68 | EPWMXBAR6 | Enable | Low |
69 | EPWMXBAR7 | Enable | Low |
70 | EPWMXBAR8 | Enable | Low |
71 | INPUTXBAR1 | Enable | Low |
72 | INPUTXBAR2 | Enable | Low |
73 | INPUTXBAR3 | Enable | Low |
74 | INPUTXBAR4 | Enable | Low |
75 | INPUTXBAR5 | Enable | Low |
76 | INPUTXBAR6 | Enable | Low |
77 | INPUTXBAR7 | Enable | Low |
78 | INPUTXBAR8 | Enable | Low |
79 | INPUTXBAR9 | Enable | Low |
80 | INPUTXBAR10 | Enable | Low |
81 | INPUTXBAR11 | Enable | Low |
82 | INPUTXBAR12 | Enable | Low |
83 | INPUTXBAR13 | Enable | Low |
84 | INPUTXBAR14 | Enable | Low |
85 | INPUTXBAR15 | Enable | Low |
86 | INPUTXBAR16 | Enable | Low |
87 | CPUx_CPUSTAT | Disable | Low |
88 | CPUx_DBGACK | Disable | High |
89 | CPUx_NMI | Disable | High |
90 | CMPSS1_CTRIPH_OR_CTRIPL | Enable | High |
91 | CMPSS2_CTRIPH_OR_CTRIPL | Enable | High |
92 | CMPSS3_CTRIPH_OR_CTRIPL | Enable | High |
93 | CMPSS4_CTRIPH_OR_CTRIPL | Enable | High |
94-105 | Reserved | ||
106 | ADCAINT1 | Disable | High |
107 | ADCAINT2 | Disable | High |
108 | ADCAINT3 | Disable | High |
109 | ADCAINT4 | Disable | High |
110-113 | Reserved | ||
114 | ADCCINT1 | Disable | High |
115 | ADCCINT2 | Disable | High |
116 | ADCCINT3 | Disable | High |
117 | ADCCINT4 | Disable | High |
118-121 | Reserved | ||
122 | HIC_nOE | Disable | High |
123 | HIC_nWE | Disable | High |
124 | HIC_nRDY | Enable | High |