SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
Table 3-249 lists the memory-mapped registers for the MEM_CFG_REGS registers. All register offset addresses not listed in Table 3-249 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | DxLOCK | Dedicated RAM Config Lock Register | EALLOW | Go |
2h | DxCOMMIT | Dedicated RAM Config Lock Commit Register | EALLOW | Go |
8h | DxACCPROT0 | Dedicated RAM Config Register | EALLOW | Go |
10h | DxTEST | Dedicated RAM TEST Register | EALLOW | Go |
12h | DxINIT | Dedicated RAM Init Register | EALLOW | Go |
14h | DxINITDONE | Dedicated RAM InitDone Status Register | Go | |
16h | DxRAMTEST_LOCK | Lock register to Dx RAM TEST registers | Go | |
20h | LSxLOCK | Local Shared RAM Config Lock Register | EALLOW | Go |
22h | LSxCOMMIT | Local Shared RAM Config Lock Commit Register | EALLOW | Go |
2Ah | LSxACCPROT1 | Local Shared RAM Config Register 1 | EALLOW | Go |
30h | LSxTEST | Local Shared RAM TEST Register | EALLOW | Go |
32h | LSxINIT | Local Shared RAM Init Register | EALLOW | Go |
34h | LSxINITDONE | Local Shared RAM InitDone Status Register | Go | |
36h | LSxRAMTEST_LOCK | Lock register to LSx RAM TEST registers | Go | |
40h | GSxLOCK | Global Shared RAM Config Lock Register | EALLOW | Go |
42h | GSxCOMMIT | Global Shared RAM Config Lock Commit Register | EALLOW | Go |
48h | GSxACCPROT0 | Global Shared RAM Config Register 0 | EALLOW | Go |
50h | GSxTEST | Global Shared RAM TEST Register | EALLOW | Go |
52h | GSxINIT | Global Shared RAM Init Register | EALLOW | Go |
54h | GSxINITDONE | Global Shared RAM InitDone Status Register | Go | |
56h | GSxRAMTEST_LOCK | Lock register to GSx RAM TEST registers | Go | |
A0h | ROM_LOCK | ROM Config Lock Register | Go | |
A2h | ROM_TEST | ROM TEST Register | Go | |
A4h | ROM_FORCE_ERROR | ROM Force Error register | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-250 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
DxLOCK is shown in Figure 3-218 and described in Table 3-251.
Return to the Summary Table.
Dedicated RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | LOCK_M1 | LOCK_M0 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LOCK_M1 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. Reset type: SYSRSn |
0 | LOCK_M0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. Reset type: SYSRSn |
DxCOMMIT is shown in Figure 3-219 and described in Table 3-252.
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Dedicated RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | COMMIT_M1 | COMMIT_M0 | |||
R-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | COMMIT_M1 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for M1 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
0 | COMMIT_M0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for M0 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed based on value of lock field in DxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
DxACCPROT0 is shown in Figure 3-220 and described in Table 3-253.
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Dedicated RAM Config Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_M1 | FETCHPROT_M1 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_M0 | FETCHPROT_M0 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23-18 | RESERVED | R | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_M1 | R/W | 0h | CPU WR Protection For M1 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
8 | FETCHPROT_M1 | R/W | 0h | Fetch Protection For M1 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_M0 | R/W | 0h | CPU WR Protection For M0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are block. Reset type: SYSRSn |
0 | FETCHPROT_M0 | R/W | 0h | Fetch Protection For M0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
DxTEST is shown in Figure 3-221 and described in Table 3-254.
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Dedicated RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | TEST_M1 | TEST_M0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | TEST_M1 | R/W | 0h | Selects the defferent modes for M1 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
1-0 | TEST_M0 | R/W | 0h | Selects the defferent modes for M0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to ECC bits. 10: Writes are allowed to ECC bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
DxINIT is shown in Figure 3-222 and described in Table 3-255.
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Dedicated RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | INIT_M1 | INIT_M0 | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | INIT_M1 | R-0/W1S | 0h | RAM Initialization control for M1 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
0 | INIT_M0 | R-0/W1S | 0h | RAM Initialization control for M0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
DxINITDONE is shown in Figure 3-223 and described in Table 3-256.
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Dedicated RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | INITDONE_M1 | INITDONE_M0 | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | INITDONE_M1 | R | 0h | RAM Initialization status for M1 RAM: 0: RAM Initialization is not done. 1: RAM Initialization has completed. Reset type: SYSRSn |
0 | INITDONE_M0 | R | 0h | RAM Initialization status for M0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
DxRAMTEST_LOCK is shown in Figure 3-224 and described in Table 3-257.
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Lock register to Dx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||||||||||
R-0/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | M1 | M0 | |||||||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | M1 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M1 field. 1: Blocks writes to DxTEST.TEST_M1 field Reset type: SYSRSn |
0 | M0 | R/W | 0h | 0: Allows writes to DxTEST.TEST_M0 field. 1: Blocks writes to DxTEST.TEST_M0 field Reset type: SYSRSn |
LSxLOCK is shown in Figure 3-225 and described in Table 3-258.
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Local Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LOCK_LS7 | LOCK_LS6 | LOCK_LS5 | LOCK_LS4 | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | LOCK_LS7 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS7 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. Reset type: SYSRSn |
6 | LOCK_LS6 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS6 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. Reset type: SYSRSn |
5 | LOCK_LS5 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS5 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. Reset type: SYSRSn |
4 | LOCK_LS4 | R/W | 0h | Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS4 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
LSxCOMMIT is shown in Figure 3-226 and described in Table 3-259.
Return to the Summary Table.
Local Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMMIT_LS7 | COMMIT_LS6 | COMMIT_LS5 | COMMIT_LS4 | RESERVED | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | COMMIT_LS7 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS7 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
6 | COMMIT_LS6 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS6 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
5 | COMMIT_LS5 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS5 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
4 | COMMIT_LS4 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, program or data memory select, initialization control and test register fields for LS4 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed based on value of lock field in LSxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | RESERVED | R/WSonce | 0h | Reserved |
0 | RESERVED | R/WSonce | 0h | Reserved |
LSxACCPROT1 is shown in Figure 3-227 and described in Table 3-260.
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Local Shared RAM Config Register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPUWRPROT_LS7 | FETCHPROT_LS7 | |||||
R-0h | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CPUWRPROT_LS6 | FETCHPROT_LS6 | |||||
R-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPUWRPROT_LS5 | FETCHPROT_LS5 | |||||
R-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CPUWRPROT_LS4 | FETCHPROT_LS4 | |||||
R-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | CPUWRPROT_LS7 | R/W | 0h | CPU WR Protection For LS7 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
24 | FETCHPROT_LS7 | R/W | 0h | Fetch Protection For LS7 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
23-18 | RESERVED | R | 0h | Reserved |
17 | CPUWRPROT_LS6 | R/W | 0h | CPU WR Protection For LS6 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
16 | FETCHPROT_LS6 | R/W | 0h | Fetch Protection For LS6 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
15-10 | RESERVED | R | 0h | Reserved |
9 | CPUWRPROT_LS5 | R/W | 0h | CPU WR Protection For LS5 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
8 | FETCHPROT_LS5 | R/W | 0h | Fetch Protection For LS5 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
7-2 | RESERVED | R | 0h | Reserved |
1 | CPUWRPROT_LS4 | R/W | 0h | CPU WR Protection For LS4 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_LS4 | R/W | 0h | Fetch Protection For LS4 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
LSxTEST is shown in Figure 3-228 and described in Table 3-261.
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Local Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEST_LS7 | TEST_LS6 | TEST_LS5 | TEST_LS4 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-14 | TEST_LS7 | R/W | 0h | Selects the defferent modes for LS7 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
13-12 | TEST_LS6 | R/W | 0h | Selects the defferent modes for LS6 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
11-10 | TEST_LS5 | R/W | 0h | Selects the defferent modes for LS5 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
9-8 | TEST_LS4 | R/W | 0h | Selects the defferent modes for LS4 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | RESERVED | R/W | 0h | Reserved |
1-0 | RESERVED | R/W | 0h | Reserved |
LSxINIT is shown in Figure 3-229 and described in Table 3-262.
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Local Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INIT_LS7 | INIT_LS6 | INIT_LS5 | INIT_LS4 | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | INIT_LS7 | R-0/W1S | 0h | RAM Initialization control for LS7 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
6 | INIT_LS6 | R-0/W1S | 0h | RAM Initialization control for LS6 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
5 | INIT_LS5 | R-0/W1S | 0h | RAM Initialization control for LS5 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
4 | INIT_LS4 | R-0/W1S | 0h | RAM Initialization control for LS4 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | RESERVED | R-0/W1S | 0h | Reserved |
0 | RESERVED | R-0/W1S | 0h | Reserved |
LSxINITDONE is shown in Figure 3-230 and described in Table 3-263.
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Local Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INITDONE_LS7 | INITDONE_LS6 | INITDONE_LS5 | INITDONE_LS4 | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RESERVED | R | 0h | Reserved |
7 | INITDONE_LS7 | R | 0h | RAM Initialization status for LS7 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
6 | INITDONE_LS6 | R | 0h | RAM Initialization status for LS6 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
5 | INITDONE_LS5 | R | 0h | RAM Initialization status for LS5 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
4 | INITDONE_LS4 | R | 0h | RAM Initialization status for LS4 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | RESERVED | R | 0h | Reserved |
LSxRAMTEST_LOCK is shown in Figure 3-231 and described in Table 3-264.
Return to the Summary Table.
Lock register to LSx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||||||||||
R-0/W-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LS7 | LS6 | LS5 | LS4 | RESERVED | RESERVED | RESERVED | RESERVED | |||||||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-8 | RESERVED | R | 0h | Reserved |
7 | LS7 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS7 field. 1: Blocks writes to LSxTEST.TEST_LS7 field. Reset type: SYSRSn |
6 | LS6 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS6 field. 1: Blocks writes to LSxTEST.TEST_LS6 field. Reset type: SYSRSn |
5 | LS5 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS5 field. 1: Blocks writes to LSxTEST.TEST_LS5 field. Reset type: SYSRSn |
4 | LS4 | R/W | 0h | 0: Allows writes to LSxTEST.TEST_LS4 field. 1: Blocks writes to LSxTEST.TEST_LS4 field. Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
GSxLOCK is shown in Figure 3-232 and described in Table 3-265.
Return to the Summary Table.
Global Shared RAM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | LOCK_GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | LOCK_GS0 | R/W | 0h | Locks the write to access protection, master select, initialization control and test register fields for GS0 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed. 1: Write to ACCPROT, TEST, INIT and Mselect fields are blocked. Reset type: SYSRSn |
GSxCOMMIT is shown in Figure 3-233 and described in Table 3-266.
Return to the Summary Table.
Global Shared RAM Config Lock Commit Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | COMMIT_GS0 |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R/WSonce | 0h | Reserved |
14 | RESERVED | R/WSonce | 0h | Reserved |
13 | RESERVED | R/WSonce | 0h | Reserved |
12 | RESERVED | R/WSonce | 0h | Reserved |
11 | RESERVED | R/WSonce | 0h | Reserved |
10 | RESERVED | R/WSonce | 0h | Reserved |
9 | RESERVED | R/WSonce | 0h | Reserved |
8 | RESERVED | R/WSonce | 0h | Reserved |
7 | RESERVED | R/WSonce | 0h | Reserved |
6 | RESERVED | R/WSonce | 0h | Reserved |
5 | RESERVED | R/WSonce | 0h | Reserved |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | RESERVED | R/WSonce | 0h | Reserved |
1 | RESERVED | R/WSonce | 0h | Reserved |
0 | COMMIT_GS0 | R/WSonce | 0h | Permanently Locks the write to access protection, master select, initialization control and test register fields for GS0 RAM: 0: Write to ACCPROT, TEST, INIT and Mselect fields are allowed based on value of lock field in GSxLOCK register. 1: Write to ACCPROT, TEST, INIT and Mselect fields are permanently blocked. Reset type: SYSRSn |
GSxACCPROT0 is shown in Figure 3-234 and described in Table 3-267.
Return to the Summary Table.
Global Shared RAM Config Register 0
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HICWRPROT_GS0 | DMAWRPROT_GS0 | CPUWRPROT_GS0 | FETCHPROT_GS0 | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Reserved |
26 | RESERVED | R/W | 0h | Reserved |
25 | RESERVED | R/W | 0h | Reserved |
24 | RESERVED | R/W | 0h | Reserved |
23-19 | RESERVED | R | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7-4 | RESERVED | R | 0h | Reserved |
3 | HICWRPROT_GS0 | R/W | 0h | HICA WR Protection For GS0 RAM: 0: HICA Writes are allowed. 1: HICA Writes are blocked. Reset type: SYSRSn |
2 | DMAWRPROT_GS0 | R/W | 0h | DMA WR Protection For GS0 RAM: 0: DMA Writes are allowed. 1: DMA Writes are blocked. Reset type: SYSRSn |
1 | CPUWRPROT_GS0 | R/W | 0h | CPU WR Protection For GS0 RAM: 0: CPU Writes are allowed. 1: CPU Writes are blocked. Reset type: SYSRSn |
0 | FETCHPROT_GS0 | R/W | 0h | Fetch Protection For GS0 RAM: 0: CPU Fetch are allowed. 1: CPU Fetch are blocked. Reset type: SYSRSn |
GSxTEST is shown in Figure 3-235 and described in Table 3-268.
Return to the Summary Table.
Global Shared RAM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | TEST_GS0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R/W | 0h | Reserved |
29-28 | RESERVED | R/W | 0h | Reserved |
27-26 | RESERVED | R/W | 0h | Reserved |
25-24 | RESERVED | R/W | 0h | Reserved |
23-22 | RESERVED | R/W | 0h | Reserved |
21-20 | RESERVED | R/W | 0h | Reserved |
19-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R/W | 0h | Reserved |
15-14 | RESERVED | R/W | 0h | Reserved |
13-12 | RESERVED | R/W | 0h | Reserved |
11-10 | RESERVED | R/W | 0h | Reserved |
9-8 | RESERVED | R/W | 0h | Reserved |
7-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | RESERVED | R/W | 0h | Reserved |
1-0 | TEST_GS0 | R/W | 0h | Selects the defferent modes for GS0 RAM: 00: Functional Mode. 01: Writes are allowed to data bits only. No write to parity bits. 10: Writes are allowed to parity bits only. No write to data bits. 11: Functional Mode. Reset type: SYSRSn |
GSxINIT is shown in Figure 3-236 and described in Table 3-269.
Return to the Summary Table.
Global Shared RAM Init Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | INIT_GS0 |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R-0/W1S | 0h | Reserved |
14 | RESERVED | R-0/W1S | 0h | Reserved |
13 | RESERVED | R-0/W1S | 0h | Reserved |
12 | RESERVED | R-0/W1S | 0h | Reserved |
11 | RESERVED | R-0/W1S | 0h | Reserved |
10 | RESERVED | R-0/W1S | 0h | Reserved |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | RESERVED | R-0/W1S | 0h | Reserved |
5 | RESERVED | R-0/W1S | 0h | Reserved |
4 | RESERVED | R-0/W1S | 0h | Reserved |
3 | RESERVED | R-0/W1S | 0h | Reserved |
2 | RESERVED | R-0/W1S | 0h | Reserved |
1 | RESERVED | R-0/W1S | 0h | Reserved |
0 | INIT_GS0 | R-0/W1S | 0h | RAM Initialization control for GS0 RAM: 0: None. 1: Start RAM Initialization. Reset type: SYSRSn |
GSxINITDONE is shown in Figure 3-237 and described in Table 3-270.
Return to the Summary Table.
Global Shared RAM InitDone Status Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | INITDONE_GS0 |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | RESERVED | R | 0h | Reserved |
14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R | 0h | Reserved |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | 0h | Reserved |
10 | RESERVED | R | 0h | Reserved |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | RESERVED | R | 0h | Reserved |
5 | RESERVED | R | 0h | Reserved |
4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | INITDONE_GS0 | R | 0h | RAM Initialization status for GS0 RAM: 0: RAM Initialization is not done. 1: RAM Initialization is done. Reset type: SYSRSn |
GSxRAMTEST_LOCK is shown in Figure 3-238 and described in Table 3-271.
Return to the Summary Table.
Lock register to GSx RAM TEST registers
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | GS0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | GS0 | R/W | 0h | 0: Allows writes to GSxTEST.TEST_GS0 field. 1: Blocks writes to GSxTEST.TEST_GS0 field. Reset type: SYSRSn |
ROM_LOCK is shown in Figure 3-239 and described in Table 3-272.
Return to the Summary Table.
ROM Config Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | LOCK_SECUREROM | LOCK_BOOTROM | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | A value of 0xa5a5 to this field is simultaneously required for the writes to the rest of the fields of this register to succeed, Reset type: SYSRSn |
15-3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LOCK_SECUREROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of SECUREROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
0 | LOCK_BOOTROM | R/W | 0h | Locks write access to test control fields (TEST and FORCE_ERROR) of BOOTROM 0: Write access allowed 1: Write access blocked Reset type: SYSRSn |
ROM_TEST is shown in Figure 3-240 and described in Table 3-273.
Return to the Summary Table.
ROM TEST Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | TEST_SECUREROM | TEST_BOOTROM | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | 0h | Reserved |
5-4 | RESERVED | R/W | 0h | Reserved |
3-2 | TEST_SECUREROM | R/W | 0h | Selects the different modes for SECUREROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
1-0 | TEST_BOOTROM | R/W | 0h | Selects the different modes for BOOTROM: 00: Functional Mode. 01: same as '00' but Parity check on data read is disabled (for debug) 10: Parity Bits are visible on memory map (for debug) 11: Same as '00' but NMI is not generated on errors, used for diagnostics. (for diagnostics) Reset type: SYSRSn |
ROM_FORCE_ERROR is shown in Figure 3-241 and described in Table 3-274.
Return to the Summary Table.
ROM Force Error register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | FORCE_SECUREROM_ERROR | FORCE_BOOTROM_ERROR | ||||
R-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-3 | RESERVED | R | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | FORCE_SECUREROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |
0 | FORCE_BOOTROM_ERROR | R/W | 0h | Force parity error by feeding inverted Parity bit to Parity checking logic. Reset type: SYSRSn |