SPMU411 November   2025 TPS65215-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521570-Q1 Power Sequence and Example Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  6. 3Revision History

2.7 Over-Current Deglitch

This section describes the default settings for the over current deglitch. When any of these registers are set (value = 1b), it enabled the long-deglitch option for the corresponding rail.

Table 2-14 Over Current Deglitch
Register NameField NameValueDescription
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_BUCK10x0Deglitch duration for OverCurrent on BUCK1 is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_BUCK20x0Deglitch duration for OverCurrent on BUCK2 is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_BUCK30x0Deglitch duration for OverCurrent on BUCK3 is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_LDO10x0Deglitch duration for OverCurrent on LDO1 is ~20us
OC_DEGL_CONFIGEN_LONG_DEGL_FOR_OC_LDO20x0Deglitch duration for OverCurrent on LDO3 is ~20us