SPMU411 November   2025 TPS65215-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521570-Q1 Power Sequence and Example Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  6. 3Revision History

2.4.1 Power Sequence Settings - Slot assignments

Table 2-6 Power-UP Sequence Settings - Slot Assignments
Register NameField NameValueDescription
BUCK1BUCK1_SEQUENCE_SLOTBUCK1_SEQUENCE_ON_SLOT0x4slot 4
BUCK2BUCK2_SEQUENCE_SLOTBUCK2_SEQUENCE_ON_SLOT0x2slot 2
BUCK3BUCK3_SEQUENCE_SLOTBUCK3_SEQUENCE_ON_SLOT0x3slot 3
LDO1LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_ON_SLOT0x0slot 0
LDO2LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_ON_SLOT0x2slot 2
GPO1GPO1_SEQUENCE_SLOTGPO1_SEQUENCE_ON_SLOT0x0slot 0
GPO2GPO2_SEQUENCE_SLOTGPO2_SEQUENCE_ON_SLOT0x0slot 0
GPIOGPIO_SEQUENCE_SLOTGPIO_SEQUENCE_ON_SLOT0x0slot 0
nRSTOUTnRST_SEQUENCE_SLOT nRST_SEQUENCE_ON_SLOT0x8slot 8

Note: PMIC rails are turned ON during the power-up sequence if the corresponding EN bit on section "Enable Setting" is set to 0x01.

Table 2-7 Power-Down Sequence Settings - Slot Assignments
Register NameField NameValueDescription
BUCK1BUCK1_SEQUENCE_SLOTBUCK1_SEQUENCE_OFF_SLOT0x1slot 1
BUCK2BUCK2_SEQUENCE_SLOTBUCK2_SEQUENCE_OFF_SLOT0x3slot 3
BUCK3BUCK3_SEQUENCE_SLOTBUCK3_SEQUENCE_OFF_SLOT0x2slot 2
LDO1LDO1_SEQUENCE_SLOT LDO1_SEQUENCE_OFF_SLOT0x4slot 4
LDO2LDO2_SEQUENCE_SLOT LDO2_SEQUENCE_OFF_SLOT0x3slot 3
GPO1GPO1_SEQUENCE_SLOTGPO_SEQUENCE_OFF_SLOT0x0slot 0
GPO2GPO2_SEQUENCE_SLOTGPO2_SEQUENCE_OFF_SLOT0x0slot 0
GPIOGPIO_SEQUENCE_SLOTGPIO_SEQUENCE_OFF_SLOT0x0slot 0
nRSTOUTnRST_SEQUENCE_SLOT nRST_SEQUENCE_OFF_SLOT0x0slot 0