SPMU411 November   2025 TPS65215-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521570-Q1 Power Sequence and Example Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  6. 3Revision History

2.1 Device ID

This section lists all the register settings to identify the supported temperature and the NVM ID with the corresponding revision that represent a list of default register settings.

Table 2-1 Device ID
Register NameField NameValueDescription
TI_DEV_IDTI_DEVICE_ID0x95Device specific ID code to identify supported ambient and junction temperature.
NVM_IDTI_NVM_ID0x46Identification code for the NVM ID
FACTORY_CONFIG_2NVM_REVISION0x0Identification code for the NVM revision
I2C_ADDRESS_REGI2C_ADDRESS0x30I2C address