SPMU411 November   2025 TPS65215-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521570-Q1 Power Sequence and Example Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  6. 3Revision History

2.3 Regulator Voltage Settings

This section describes how each of the PMIC power resources were configured.

Table 2-4 Buck Regulator Settings
PMIC RailRegister NameField NameValueDescription
Bucks Switching Mode

(Global for all Buck regulators)

BUCKS_CONFIGBUCK_FF_ENABLE0x0Quasi-fixed frequency mode
BUCKS_CONFIGBUCK_SS_ENABLE0x0Spread spectrum disabled
BUCK1BUCK1_VOUTBUCK1_VSET0xA0.850V
BUCK1_VOUTBUCK1_UV_THR_SEL0x0-5% UV detection
BUCK1_VOUTBUCK1_BW_SEL 0x1high bandwidth
BUCK2BUCK2_VOUT BUCK2_VSET0x241.800V
BUCK2_VOUT BUCK2_UV_THR_SEL 0x0-5% UV detection
BUCK2_VOUT BUCK2_BW_SEL 0x0low bandwidth
BUCKS_CONFIGBUCK2_PHASE_CONFIG0x3270 degrees
BUCK3BUCK3_VOUTBUCK3_VSET0x141.100V
BUCK3_VOUTBUCK3_UV_THR_SEL0x0-5% UV detection
BUCK3_VOUTBUCK3_BW_SEL 0x0low bandwidth
BUCKS_CONFIGBUCK3_PHASE_CONFIG0x2180 degrees

Note:
  • When Bucks are configured for quasi-fixed frequency (BUCK_FF_ENABLE=0x0), changing the switching mode between auto-PFM and forced-PWM can be triggered by I2C (MODE_I2C_CTRL) or with one of the multi-function pins (MODE/RESET or MODE/STBY) if one of them is configured as MODE. "Forced PWM" has priority over "Auto PFM".
  • "BUCK2_PHASE_CONFIG", "BUCK3_PHASE_CONFIG" and "BUCK_SS_ENABLE" are only applicable when the Buck regulators are configured for fixed frequency (BUCK_FF_ENABLE=0x1).

Table 2-5 LDO Regulator Settings
PMIC RailSettingRegister NameField NameValueDescription
LDO1LDO1 output voltageLDO1_VOUTLDO1_VSET0x363.300V
LDO1 configurationLDO1_VOUTLDO1_LSW_CONFIG0x0Not Applicable (LDO1 not configured as load-switch)
LDO1_VOUTLDO1_BYP_CONFIG0x0LDO1 configured as LDO
LDO1 UV thresholdGENERAL_CONFIGLDO1_UV_THR0x0-5% UV detection
LDO2LDO2 output voltageLDO2_VOUT LDO2_VSET0x181.800V
LDO2 configurationLDO2_VOUT LDO2_LSW_CONFIG0x0LDO Mode
LDO ramp configurationLDO2_VOUT LDO2_SLOW_PU_RAMP0x1Slow ramp for power-up (~3ms)
LDO2 UV thresholdGENERAL_CONFIGLDO2_UV_THR0x0-5% UV detection
Note:
  • If a LDO is configured in bypass-mode or LSW-mode, UV-detection is not supported.
  • If an LDO is configured in bypass-mode, the corresponding PVIN_LDOx supply must match the configured output voltage in the LDOx_VOUT register.
  • If LDO is configured as load-switch (LSW_mode), the desired voltage does not need to be configured in the LDOx_VOUT register.
  • In bypass- or LSW-mode, the LDO acts as a switch, where VOUT is VIN minus the drop over the FET-resistance.
  • If LDO1 is configured as bypass, it allows voltage and function changes between LDO (VOUT=1.8V) and VOUT=VSET register setting. This voltage/function change can be triggered by hardware (using the VSEL_SD pin when configured as SD) or by software (VSEL_SD_I2C_CTRL).