SPMU411 November   2025 TPS65215-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521570-Q1 Power Sequence and Example Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  6. 3Revision History

2.8 Mask Settings

This section describes the settings that are masked by default and the effect they have on the device state as well as the nINT pin.

Table 2-15 Mask Settings
Register NameField NameValueDescription
Mask effects on device state and nINT pinMASK_CONFIGMASK_EFFECT0x3no state change, nINT reaction, bit set for Faults (same as 10b)
UV MaskINT_MASK_UVBUCK1_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVBUCK2_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVBUCK3_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVLDO1_UV_MASK0x0un-masked (Faults reported)
INT_MASK_UVLDO2_UV_MASK0x0un-masked (Faults reported)
Power-up retries/attemptsINT_MASK_UVMASK_RETRY_COUNT0x0Device retries up to 2 times
Die TemperatureMASK_CONFIGSENSOR_0_WARM_MASK0x0un-masked (Faults reported)
MASK_CONFIGSENSOR_1_WARM_MASK0x0un-masked (Faults reported)
MASK_CONFIGSENSOR_2_WARM_MASK0x0un-masked (Faults reported)
MASK_CONFIGSENSOR_3_WARM_MASK0x0un-masked (Faults reported)
Masking bit to control whether nINT pin is sensitive to PushButton (PB)MASK_CONFIGMASK_INT_FOR_PB0x1masked (nINT pin not sensitive to any PB events)
Masking bit to control whether nINT pin is sensitive to RV (Residual Voltage) MASK_CONFIGMASK_INT_FOR_RV0x0un-masked (nINT pin pulled low for any RV events during transition to ACTIVE state or during enabling of rails)