SPMU411 November   2025 TPS65215-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1Introduction
  5. 2EEPROM Device Settings
    1. 2.1  Device ID
    2. 2.2  Enable Settings
    3. 2.3  Regulator Voltage Settings
    4. 2.4  Power Sequence Settings
      1. 2.4.1 Power Sequence Settings - Slot assignments
      2. 2.4.2 Power Sequence Settings - Slot Durations
      3. 2.4.3 TPS6521570-Q1 Power Sequence and Example Block Diagram
    5. 2.5  EN / PB / VSENSE Settings
    6. 2.6  Multi-Function Pin Settings
    7. 2.7  Over-Current Deglitch
    8. 2.8  Mask Settings
    9. 2.9  Discharge Check
    10. 2.10 Multi PMIC Config
  6. 3Revision History

2.10 Multi PMIC Config

The TPS6521570-Q1 allows to synchronize multiple devices, in case more rails are required to be supplied. The GPIO (pin#16) is an input/output digital pin, however, the input-functionality is only used in multi-PMIC configuration. The I/O-configuration of the GPIO-pin is done by the MULTI_DEVICE_ENABLE bit in MFP_1_CONFIG register. The table below shows the default multi-device register setting. For more information about the TPS6521570-Q1 multi-PMIC operation, please refer to the device data sheet available on ti.com.

Table 2-17 Multi-PMIC Configuration
Register NameField NameValueDescription
MFP_1_CONFIGMULTI_DEVICE_ENABLE0x0Single-device configuration, GPIO pin configured as GPO