3.2.2 BIST Procedure

The following steps will explain how BIST is conducted between the DS90UB953-Q1 and DS90UB954-Q1. After basic rules have been followed, BIST will determine the health of the link between the SER and DES only. Example code is listed in Section 7.1.1 and a list of registers used in the code is shown in Table 16 and Table 17.

1. Use the reset register to reset the entire digital block and set the serializer (SER) and deserializer (DES) to a known state.
   • Register 0x01 is the RESET_CTL register on both the 953 and 954.
   • Note that bit [0] in REST_CTL does not reset the registers. Bit [1] controls the digital reset responsible for clearing registers. Generally, it is better to conduct a digital reset without clearing the registers to save time initial troubleshooting steps.

Table 14. DEVICE_STS Register Description on 954

ADDR.	0x04[7]	0x04[7]	0x04[7]	0x04[7]	0x04[7]	0x04[7]	0x04[1:0]
Bits	X	X	X	X	1	1	XX
Desc.	Configuration Checksum Passed	Power-up Initialization Complete	Reserved	REFCLK Valid	PASS Status	LOCK Status	Reserved

Table 15. GENERAL_STATUS Register Description for Lock on 953

ADDR.	0x52[7]	0x52[6]	0x52[5]	0x52[4]	0x52[3]	0x52[2]	0x52[1]	0x52[0]
Bits	X	1	X	X	X	1	X	1
Desc.	Reserved	LOCK Status	Reserved	BC Link lost	BIST Error detected	FC High-speed lock detected	BC error detected	BC Link detected

2. Confirm that SER and DES are locked by accessing the respective devices IDs and DES device status.
   • As mentioned before, verifying the correct SER and DES device IDs indicates that the correct DES device ID and SER alias ID is used when making I2C commands. The DEVICE_ID for both devices can be found in register 0x00 while the SER_ALIAS_ID can be found on the deserializer in register 0x5C.
   • The DES device status will indicate if the LOCK status is high. As mentioned before, the LOCK status serves the purpose of validating the link integrity of the connection between the SER and DES. When the LOCK status is high, the PLL in the DES is locked and validates the data and clock recovered from the serial input. As a result, the value should be 0xCF. DEVICE_STS on the 954 can be found in register 0x04.
3. Enable the write permission for RX Port0.
   • On the DES, this bit allows data to be written to RX port 0 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 Receiver port registers. Remember, configuring parameters that pertain to RX port 0 registers require a write command. If permission to write RX port 0 is not given, then register values will not be changed even with correct write commands. The FPD3_PORT_SEL can be found in register 0x4C.
4. On the SER, clear any previous errors in the system before enabling BIST by clearing the CRC errors and BIST CRC errors in addition to reading the BCC status and SER general status.
   • BIST CRC errors and CRC errors are cleared to ensure that the next BIST test only includes errors from the specified test. These errors are housed in the BC_CTRL register located at 0x49 on the 953. Value 0x28 selects the self-clearing bits to clear the BIST CRC and CRC errors.
   • Reading the bidirectional control channel (BCC) status has two functions. First, if there are any errors that occurred over the BCC, they may be flagged and categorized in this register. Second, reading this register may clear a flag that is raised in the SER general status register that can only be cleared when the BCC status register is read. The BCC_STATUS register is located at 0x79 on the 953.
   • The general status of the SER holds indicators for many different types of errors, including BIST CRC ERR and the RX LOCK DETECT. Verifying its value before BIST will show the changes that occur after BIST. A typical general status will indicate the value 0x45 showing that RX Lock Detect, HS PLL Lock, and Link Detect flags are high. GENERAL_STS can be found at register 0x52 on the 953.
5. Read the BIST error counter before BIST.
   • In addition to checking the indicator if an error occurred, it is important to read the number errors before the test. If one error is forced, we expect this value to be 0x01 after the BIST has completed. The BIST_ERR_CNT can be found in register 0x54 of the 953.
6. On the DES, read the BIST control register, enable the BIST, force the singular, multiple, or no errors, and read the RX port status after the BIST starts and before the BIST ends.
   • The BIST control register enables the BIST as well as various parameters important for BIST. Bit [0] of the BIST control represents BIST_EN. Reading it before and then after enabling BIST helps show that BIST has been enabled. By using the sleep command, BIST can run as long as the user desires. BIST_CTL can be located in register 0xB3 of the 954.
   • The RX port status, like the general status and BCC status on the 954, houses many useful error flags. These flags include: the BCC CRC error, lock status change, BCC sequence error, parity error, receiver pass indication, lock status, and locked to recovered clock status. Consider bit [4] which indicates the LOCK_STS_CHG. By reading this value right after the BIST is enabled, and right before the BIST is disabled, the user is able to tell if the lock status changed during BIST. It is important to read this register after BIST is started because enabling and disabling the BIST forces the devices to relock. RX_PORT_STS1 can be found in register 0x4D.
   • The port debug register is used for debugging various functions by enabling build in errors or tests. Bit [0] is self-clearing and controls the FORCE_ONE_BC_ERROR function. Bit [1], by comparison, controls FORCE_BC_ERRORS and must be cleared. This is helpful for testing the error detection of the system. The PORT_DEBUG register can be found at 0xD0 of the 954.
7. Disable the BIST and write permissions of RX Port0.
   • Disabling the BIST is done through the BIST control register, 0xB3, on the DES. BIST uses all functionality of the BCC and disabling the BIST reestablishes communication between the SER and DES.
   • This bit allows data to be written to RX port 0 registers. Any combination of RX port registers can be written simultaneously. This applies to all paged FPD3 Receiver port registers. Because only reads are required at this stage the BIST, it is good practice to disable the write permission. The FPD3_PORT_SEL can be found in register 0x4C.
8. Check for errors on the SER general status, DES device status, and BIST error count.
   • The general status of the 953, with register value 0x52, that was checked before BIST gave a value of 0x45. With the introduction of an error, a value of 0x4D is read from the register. This value indicates that the RX Lock Detect, HS PLL Lock, Link Detect, and BIST CRC Error flags are high.
   • The device status of the 954 was checked before BIST. Despite forcing an error in the system, the status should read still read 0xCF because the devices should still be LOCKED.
   • Before BIST was enabled, all possible BIST CRC errors were cleared and the BIST CRC error count was read. After forcing one error during BIST, one error should be displayed in the BIST_ERR_CNT. If the count is 0x01, that means that the devices were LOCKED, any errors that occurred were only produced during the BIST test, the error detection system is working as intended, and the link between the SER and DES is not producing any errors.

The LOCK and PASS statuses ensure that the serializer and deserializer are communicating effectively. By using the built-in self test (BIST), the LOCK between devices can be accurately evaluated. As a result, this is a fundamental step to ensure proper design of the board.