SNAU271 October   2021 LMK1D1212

 

  1.   Trademarks
  2. 1 Features
  3. 2 General Description
  4. 3 Signal Path and Control Circuitry
  5. 4 Getting Started
  6. 5 Power Supply Connection
  7. 6 Input Clock Selection
    1. 6.1 Differential Input
    2. 6.2 Single-Ended Input
  8. 7 Output Clock
  9. 8 EVM Board Schematic
  10. 9 REACH Compliance
  11. 10Bill of Materials

3 Signal Path and Control Circuitry

The LMK1D1212 supports single-ended inputs up to 250 MHz and differential inputs up to 2 GHz. Each device provides up to 12 LVDS outputs that operate at the selected input frequency.

For more information, see the LMK1D1212 Low Additive Jitter LVDS Buffer data sheet (SNAS823) for details.