SNAA360 June   2022 ADC32RF54 , ADC32RF55 , AFE7950 , LMX1204

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Cascaded LMX1204 Design
  4. 2Results
    1. 2.1 Single Device Performance
    2. 2.2 Cascaded Device Performance
    3. 2.3 Detailed Results
      1. 2.3.1 1 GHz Performance
      2. 2.3.2 3 GHz Performance
      3. 2.3.3 6 GHz Performance
      4. 2.3.4 10 GHz Performance
      5. 2.3.5 12.8 GHz Performance
    4. 2.4 Cascaded LMX1204 Performance With ADC32RF54
    5. 2.5 Cascaded LMX1204 Performance With AFE7950
  5. 3Summary
  6. 4References

1 Introduction

When numerous devices in a system require a shared clock source, distributing the clock signal inadequately leads to degradation in system performance. This becomes a prevalent concern for applications utilizing digital beamforming (phased array radar, communications, ultrasound) as signal distortion increases directly as a result of increased clock jitter. The LMX1204 is a clock distribution device designed for applications requiring minimal added phase noise within the frequency range 300 MHz to 12.8 GHz. Although the LMX1204 is a high-speed clock distribution device allowing for buffered, multiplied, and divided output frequency (relative to the input frequency), this report will focus solely on the performance of this device in a buffered (1-to-1) configuration.