SLVUDM8 March   2026 TPS63820

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Background
    2. 2.2 Input and Output Connectors, Test Points, and Headers Description
      1. 2.2.1 VIN Terminal
      2. 2.2.2 S+/S– (Near the VIN Terminal)
      3. 2.2.3 GND Terminal (Near the VIN Terminal)
      4. 2.2.4 VOUT Terminal
      5. 2.2.5 S+/S– (Near the VOUT Terminal)
      6. 2.2.6 GND Terminal (Near the VOUT Terminal)
      7. 2.2.7 Test Points
        1. 2.2.7.1 LX1, LX2
        2. 2.2.7.2 SCL, SDA
      8. 2.2.8 Header Information
        1. 2.2.8.1 10-Pin Header
      9. 2.2.9 Jumper Information
        1. 2.2.9.1 Jumper EN
        2. 2.2.9.2 Jumper VSEL/ADDR
    3. 2.3 Setup
    4. 2.4 Modifications
      1. 2.4.1 IC U1 Operation
  7. 3Software
    1. 3.1 Software Setup
    2. 3.2 Interface Hardware Setup
    3. 3.3 User Interface Operation
      1. 3.3.1 Home Screen
      2. 3.3.2 Settings Screen
      3. 3.3.3 Register Map Screen
    4. 3.4 Device Registers
      1. 3.4.1 Register CONTROL (Register Address: 0x01; Default: 0xE0 or 0x40)
      2. 3.4.2 Register STATUS (Register Address: 0x02; Default: 0x00)
      3. 3.4.3 Register DEVID (Register Address: 0x03; Default: 0x20)
      4. 3.4.4 Register VOUT1 (Register Address: 0x04; Default: 0x54)
      5. 3.4.5 Register CONTROL2 (Register Address: 0x06; Default: 0x08)
  8. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Board Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks

3.4.1 Register CONTROL (Register Address: 0x01; Default: 0xE0 or 0x40)

Return to Device Registers.

Table 3-3 Register CONTROL Format
7 6 5 4 3 2 1 0
EN_DISCH EN_SCP ENABLE ULTRA_SONIC FPWM RPWM SLEW[1:0]
R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only
Table 3-4 Register CONTROL Field Descriptions
Bit Field Type Reset Description
7 EN_DISCHG R/W X Enable output discharge function.
0: output discharge function disabled (for TPS638201)
1 : Output discharge function enabled (for TPS63820)
6 EN_SCP R/W 1 Enable output short-circuit protection (Hiccup).
0: output short circuit protection disabled
1 : output short-circuit protection enabled
5 ENABLE R/W X This bit controls operation of the converter.
0 : Converter operation disabled (Start-up value for TPS638201)
1 : Converter operation enabled (Start-up value for TPS63820)
4 ULTRA_SONIC R/W 0 This bit controls the ultra-sonic mode function.
0: Ultra-sonic mode disabled
: Ultra-sonic mode enabled
3 FPWM R/W 0 This bit controls the forced-PWM function.
0: Forced-PWM operation disabled
1 : Forced-PWM operation enabled
2 RPWM R/W 0 This bit controls the ramp-PWM function.
0: Ramp-PWM operation disabled
1 : Ramp-PWM operation enabled
1:0 SLEW[1:0] R/W 00 These bits control the slew rate of the DVS function.
00: ±1V/ms
01: ±5V/ms
10: ±10V/ms
11: ±25V/ms