SLVUDM8 March   2026 TPS63820

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Background
    2. 2.2 Input and Output Connectors, Test Points, and Headers Description
      1. 2.2.1 VIN Terminal
      2. 2.2.2 S+/S– (Near the VIN Terminal)
      3. 2.2.3 GND Terminal (Near the VIN Terminal)
      4. 2.2.4 VOUT Terminal
      5. 2.2.5 S+/S– (Near the VOUT Terminal)
      6. 2.2.6 GND Terminal (Near the VOUT Terminal)
      7. 2.2.7 Test Points
        1. 2.2.7.1 LX1, LX2
        2. 2.2.7.2 SCL, SDA
      8. 2.2.8 Header Information
        1. 2.2.8.1 10-Pin Header
      9. 2.2.9 Jumper Information
        1. 2.2.9.1 Jumper EN
        2. 2.2.9.2 Jumper VSEL/ADDR
    3. 2.3 Setup
    4. 2.4 Modifications
      1. 2.4.1 IC U1 Operation
  7. 3Software
    1. 3.1 Software Setup
    2. 3.2 Interface Hardware Setup
    3. 3.3 User Interface Operation
      1. 3.3.1 Home Screen
      2. 3.3.2 Settings Screen
      3. 3.3.3 Register Map Screen
    4. 3.4 Device Registers
      1. 3.4.1 Register CONTROL (Register Address: 0x01; Default: 0xE0 or 0x40)
      2. 3.4.2 Register STATUS (Register Address: 0x02; Default: 0x00)
      3. 3.4.3 Register DEVID (Register Address: 0x03; Default: 0x20)
      4. 3.4.4 Register VOUT1 (Register Address: 0x04; Default: 0x54)
      5. 3.4.5 Register CONTROL2 (Register Address: 0x06; Default: 0x08)
  8. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 Board Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks

Description

The TPS63820EVM is used to evaluate the performance of the TPS63820. The TPS63820EVM features a highly-efficient, single-inductor, internally compensated, low quiescent current, 4A buck-boost converter in a 15-pin, 2.0mm × 1.2mm × 0.5mm DSBGA package.