SLVK327 July   2026 TPS7H1301-SP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 LETEFF and Range Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References

2 Single-Event Effects (SEE)

The primary concern for the TPS7H1301-SP is the robustness against the destructive single-event effects (DSEE): single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H1301-SP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1,2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H1301-SP was tested for SEL at the maximum recommended operating conditions of VIN=6.3V and the maximum and minimum output voltages of -6V and -0.6V, respectively. The device was loaded with a Chroma 63600 E-Load in constant resistance (CR) mode to achieve a load of 75mA during the VIN=6.3V to VOUT=-6V bias case and a load of 400mA during the VIN=6.3V to VOUT=-0.6V bias case. A load of 75mA was chosen during the VIN=6.3V to VOUT=-6V bias case rather than the full 400mA load in order to maintain VIN to VOUT headroom. During testing of the 4 production devices, the TPS7H1301-SP did not exhibit any SEL with heavy-ions with LETEFF = 75MeV·cm2/mg at flux ≈105ions/cm2/s, fluence of ≈107ions/cm2, and a die temperature of 125°C.

The TPS7H1301-SP was evaluated for SEB/SEGR at the same maximum recommended bias conditions as SEL testing. Because it has been shown that the MOSFET susceptibility to burnout decrement with temperature [5], the device was evaluated while operating under room temperatures. The device was tested with no external thermal control device. The device was also tested for SEB Off by disabling the device. During the SEB/SEGR testing, not a single current event was observed, demonstrating that the TPS7H1301-SP is SEB/SEGR-free up to LETEFF = 75MeV·cm2/mg at a flux of ≈105ions/cm2/s, fluence of ≈107ions/cm2, and a die temperature of ≈25°C.

The TPS7H1301-SP was characterized for SET at flux of ≈105ions/cm2/s , fluence of ≈107ions/cm2, and at room temperature. The device was characterized with VIN=5V, VOUT=-1.8V, and a load of 400mA for the "golden" configuration and VIN=6V, VOUT=-5V, and a load of 150mA for the "silver" configuration. Heavy-ions with LETEFF of 75MeV·cm2/mg were used to characterize the transient performance. To see the SET results of the TPS7H1301-SP, please refer to Section 8.