SLVK230 November 2025 TPS7H4102-SEP
The TPS7H4102-SEP is fabricated in the TI Linear BiCMOS 250-nm process with a back-end-of-line (BEOL) stack consisting of 4 levels of standard thickness aluminum. The total stack height from the surface of the passivation to the silicon surface is 10.04μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the degrader, copper foil, beam port window, air gap, and the BEOL stack of the TPS7H4102-SEP, the effective LET (LETEFF) at the surface of the silicon substrate and the range was determined with:
The results are shown in Table 5-1.
| Facility | ION TYPE | Beam Energy (MeV/nucleon) | ANGLE OF INCIDENCE | DEGRADER STEPS (#) | DEGRADER ANGLE | Copper Foil Width (µm) | Beam Port Window | RANGE IN SILICON (µm) | LETEFF (MeV·cm2/mg) |
|---|---|---|---|---|---|---|---|---|---|
| TAMU | 109Ag | 15 | 0 | 0 | 0 | - | 1-mil Aramica | 95.1 | 48 |
| TAMU | 165Ho | 15 | 0 | 0 | 0 | - | 1-mil Aramica | 93.9 | 75 |
| KSEE | 109Ag | 19.5 | 0 | 0 | 0 | 5 | 3-mil PEN | 89.3 | 48 |
| KSEE | 169Tm | 19.5 | 0 | 0 | 0 | 5 | 3-mil PEN | 90 | 75 |