SLVK230 November   2025 TPS7H4102-SEP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 LETEFF and Range Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Safe Operating Area (SOA) Results
    2. 7.2 Single-Event Latch-up (SEL) Results
    3. 7.3 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References

2 Single-Event Effects (SEE)

The primary concern for the TPS7H4102-SEP is the robustness against the destructive single-event effects (DSEE): single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H4102-SEP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1,2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H4102-SEP was tested for SEL at the maximum recommended operating conditions based on a SOA (safe operating area) design of experiments (DOE) of VIN of 6.5V and 3A/channel in the "high current case" and a VIN of 7V and 1.5A/channel in the "high voltage case". Output conditions were tested in two different configurations, either with each channel configured to output 1.2V or each channel configured to output 1.8V. During testing of the 4 devices, the TPS7H4102-SEP did not exhibit any SEL with heavy-ions with LETEFF = 48 MeV·cm2/mg at flux ≈105 ions/cm2/s, fluence of ≈107 ions/cm2, and a die temperature of 125°C while maintaining operating conditions within the SOA. The full SOA consisting of both TPS7H4104 and TPS7H4102 across multiple LETEFF is presented in Section 7.1.

The TPS7H4102-SEP was evaluated for SEB/SEGR at the maximum recommended input conditions based on the SOA in the enabled and disabled mode. Because it has been shown that the MOSFET susceptibility to burnout decrement with temperature [5], the device was evaluated while operating under room temperatures. The device was tested with no external thermal control device. During the SEB/SEGR testing, not a single current event was observed demonstrating that the TPS7H4102-SEP is SEB/SEGR-free up to LETEFF = 48 MeV·cm2/mg at a flux of ≈105 ions/cm2/s, fluences of ≈107 ions/cm2, and a die temperature of ≈25°C while maintaining operating conditions within the SOA. The full SOA consisting of both TPS7H4104 and TPS7H4102 across multiple LETEFF is presented in Section 7.1.

The TPS7H4102-SEP was characterized for SET at flux of ≈105 ions/cm2/s , fluences of ≈107 ions/cm2, and room temperature. The device was characterized at VIN of 3.3V for the VOUT case of 1.2V and VIN of 5V for the VOUT case of 1.8V. During all runs each channel was loaded to 3A. Heavy-ions with LETEFF of 48 MeV·cm2/mg were used to characterize the transient performance. During all testing, there were no transients recorded on any of the outputs with the trigger window set to > |3%|. For futher detail, please refer to Section 8.