SLUUDI8 March   2026 AM13E23019

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview of BSL Features
    2. 1.2 Terminology
    3. 1.3 Additional Resources
  5. 2BSL Architecture
    1. 2.1 Design
      1. 2.1.1 Timeout Feature
        1. 2.1.1.1 Interface Autodetection
        2. 2.1.1.2 Command Reception
    2. 2.2 BSL Invocation
      1. 2.2.1 Application Request
      2. 2.2.2 GPIO Based Invocation
      3. 2.2.3 Debug Mailbox Command
      4. 2.2.4 Other BSL Invocation Methods
        1. 2.2.4.1 Pre-Boot Application Verification
        2. 2.2.4.2 Blank Device Handling
    3. 2.3 Memory
      1. 2.3.1 SRAM Memory Usage
    4. 2.4 BSL NONMAIN Configuration
      1. 2.4.1  BSL Configuration ID
      2. 2.4.2  BSL Interface Pins (BLINTERFACE_PINS)
      3. 2.4.3  BSL Invoke Pin Configuration (BSLPIN_INVOKE)
      4. 2.4.4  Memory Readout Configuration
      5. 2.4.5  BSL Password
      6. 2.4.6  Application Revision Pointer
      7. 2.4.7  Security Alert Level
      8. 2.4.8  UART Baud Rate
      9. 2.4.9  I2C Target Address
      10. 2.4.10 Configuration CRC
    5. 2.5 Changing BSL Configuration
      1. 2.5.1 Using BSL Commands
      2. 2.5.2 Using Debug Interface
  6. 3Bootloader Protocol
    1. 3.1 Packet Format
    2. 3.2 BSL Protocol
      1. 3.2.1 BSL Acknowledgment
      2. 3.2.2 Peripheral Configuration
        1. 3.2.2.1 UART
        2. 3.2.2.2 I2C
        3. 3.2.2.3 MCAN
        4. 3.2.2.4 CRC
    3. 3.3 Bootloader Core Commands
      1. 3.3.1  Connection
      2. 3.3.2  Get Device Info
      3. 3.3.3  Unlock Bootloader
      4. 3.3.4  Program Data
      5. 3.3.5  Program Data Fast
      6. 3.3.6  Readback Data
      7. 3.3.7  Flash Range Erase
      8. 3.3.8  Mass Erase
      9. 3.3.9  Factory Reset
      10. 3.3.10 Standalone Verification
      11. 3.3.11 Start Application
      12. 3.3.12 Change Baud Rate
    4. 3.4 Bootloader Core Response
      1. 3.4.1 BSL Core Message
      2. 3.4.2 Detailed Error
      3. 3.4.3 Memory Readback
      4. 3.4.4 Device Info
      5. 3.4.5 Standalone Verification
    5. 3.5 Bootloader Security
      1. 3.5.1 Password Protected Commands
        1. 3.5.1.1 Security Alert
      2. 3.5.2 BSL Entry
  7. 4Sample Program Flow with Bootloader
  8. 5Revision History

2.3.1 SRAM Memory Usage

The AM13E230x BSL dynamically allocates SRAM memory based on the available SRAM size in the device. The SRAM memory layout contains the following two MAIN sections used for the bootloader's operation:

  • Data and Stack section - Used by BSL for its operation. While exiting the bootloader, these sections of the SRAM are cleared.
  • Variable Buffer Space - Buffer space used for storing the data packets received/sent during the BSL communication

The SRAM memory allocation structure is as follows:

  1. BSL Buffer Start Address: Calculated as the end address of the SRAM data section used for BootROM operation, aligned to the next 8-byte boundary.
  2. BSL Buffer End Address: Calculated as the RAM end address minus the stack size.
  3. Available Buffer Space: The space between BSL Buffer Start Address and BSL Buffer End Address is divided into two equal parts:
    1. RX Buffer: Used for receiving data packets, starts at BSL Buffer Start Address
    2. TX Buffer: Used for transmitting data packets, starts at BSL Buffer Start Address + Buffer Size

The maximum buffer size is limited to 32KB (0x7FFF bytes) due to the BSL protocol reserving 2 bytes for defining length. Even though the AM13E230x has 128KB of SRAM, only 32KB will be used for each buffer (RX and TX).

The SRAM memory allowed for read and write access by the host is BSL Buffer Start Address to [SRAM end address – Stack Size], where SRAM end address is determined by the SRAM memory available in each device. Since the same SRAM space is shared with variable buffer space, it has chances of getting overwritten during an SRAM write/read operation.