SLAA475A October   2010  – March 2019 MSP430L092

 

  1.   MSP430x09x Analog Pool: Feature Set and Advanced Use
    1.     Trademarks
    2. 1 MSP430x09x Overview
    3. 2 Analog Pool (A-Pool)
      1. 2.1  Input Dividers
      2. 2.2  Internal Reference
      3. 2.3  Starting and Stopping the A-Pool
      4. 2.4  Comparator Function
      5. 2.5  8-Bit DAC Function
      6. 2.6  8-Bit ADC Function
        1. 2.6.1 ADC Conversion Using Ramp
          1. 2.6.1.1 ADC Conversion Without Error Compensation
          2. 2.6.1.2 ADC Conversions With Overdrive Compensation
          3. 2.6.1.3 ADC Conversions With Offset Compensation
          4. 2.6.1.4 ADC Conversions With Overall Compensation
          5. 2.6.1.5 Windowed ADC Conversion
        2. 2.6.2 ADC Conversion Using SAR
        3. 2.6.3 Multiple ADC Conversions
        4. 2.6.4 Comparison Between Different Measurement Methods
        5. 2.6.5 Error Dependencies
      7. 2.7  SVM Function
      8. 2.8  Use of Multiple Features
      9. 2.9  Temperature Measurements With the A-Pool
      10. 2.10 Fractional and Integer Number Use
      11. 2.11 APINTB and APFRACTB Use With ATBU and EOCBU
      12. 2.12 A-Pool Trigger Sources
      13. 2.13 Filtering ADC Conversions With Digital Filters
    4. 3 Summary
    5. 4 References
  2.   Revision History

2.8 Use of Multiple Features

The A-Pool is not limited to providing only one of the available functions in an application. The user can decide when to provide a specific function for the application. For this, the timers or a software-based solution can be used. The following code shows a simple A/D conversion and SVM monitoring with software triggers. The observed VCC voltage is 1.25 V, and the measured channel is A0 with 500-mV range.

#include "msp430l092.h" unsigned char result; void main( void ) { // Stop watchdog timer to prevent time out reset WDTCTL = WDTPW + WDTHOLD; P1DIR |= BIT0; // Indicates VCC crosses SVM level APVDIV |= A0DIV+VCCDIVEN; // Enable VCC divider // Set 500mV input range _BIS_SR(GIE); // Switch on global interrupts APCNF = CMPON+DBON+CONVON+APREFON; // Enable comparator on + // Enable DAC buffer + // Enable conversion + // Enable reference APOMR |= CTEN; // Enable CTEN mode APIE |= EOCIE; // Enable end of conversion interrupt while(1) { APINT = 156; // Set voltage level 1250mV / 8 = 156mV APCTL = APPSEL2+APPSEL1+APNSEL2+APNSEL0+OSEL; // Set voltage divider to PSEL + // Set DAC output to NSEL + // Select output buffer SFRIFG1 &=~ SVMIFG; // Clear SVM flag APCNF |= CMPON; // Start comparison if (SFRIFG1 & SVMIFG) // Check if SVM flag is set { P1OUT ^= BIT0; // Indicates VCC crosses SVM level SFRIFG1 &=~ SVMIFG; // Clear SVM flag } APINT = 0x00; // Clear ADC-DAC-REG APCTL = CBSTP+SBSTP+APPSEL0+APPSEL2+OSEL; // Set DAC buffer output to PSEL + // Select output buffer + // Enable Comparator based stop + // Enable Saturation based stop + APCTL |= RUNSTOP; // Start conversion _BIS_SR(LPM0); // Go to LPM0 } } #pragma vector=APOOL_VECTOR // A-Pool interrupt service routine __interrupt void APOOL_ISR(void) { switch(__even_in_range(APIV,8)) // Add offset to PC and delete flag { case 0: break; case 2: result = APINT; // Save value in variable __bic_SR_register_on_exit(CPUOFF); // Exit LPM0 break; case 4: break; case 6: break; case 8: break; default: break; } }