SLAA475A October   2010  – March 2019 MSP430L092

 

  1.   MSP430x09x Analog Pool: Feature Set and Advanced Use
    1.     Trademarks
    2. 1 MSP430x09x Overview
    3. 2 Analog Pool (A-Pool)
      1. 2.1  Input Dividers
      2. 2.2  Internal Reference
      3. 2.3  Starting and Stopping the A-Pool
      4. 2.4  Comparator Function
      5. 2.5  8-Bit DAC Function
      6. 2.6  8-Bit ADC Function
        1. 2.6.1 ADC Conversion Using Ramp
          1. 2.6.1.1 ADC Conversion Without Error Compensation
          2. 2.6.1.2 ADC Conversions With Overdrive Compensation
          3. 2.6.1.3 ADC Conversions With Offset Compensation
          4. 2.6.1.4 ADC Conversions With Overall Compensation
          5. 2.6.1.5 Windowed ADC Conversion
        2. 2.6.2 ADC Conversion Using SAR
        3. 2.6.3 Multiple ADC Conversions
        4. 2.6.4 Comparison Between Different Measurement Methods
        5. 2.6.5 Error Dependencies
      7. 2.7  SVM Function
      8. 2.8  Use of Multiple Features
      9. 2.9  Temperature Measurements With the A-Pool
      10. 2.10 Fractional and Integer Number Use
      11. 2.11 APINTB and APFRACTB Use With ATBU and EOCBU
      12. 2.12 A-Pool Trigger Sources
      13. 2.13 Filtering ADC Conversions With Digital Filters
    4. 3 Summary
    5. 4 References
  2.   Revision History

2.6.1 ADC Conversion Using Ramp

The APINT counter starts at the current APINT value and counts either up or down, depending on the status of the SLOPE bit. When the comparator output signal changes, an end-of-conversion signal is generated and can be used to stop the counter (see Figure 5). The value in the APINT register is then the measured value of the input signal. When using the ramp generator method, four different methods are possible to recalculate internal offsets and errors that are coming from the A-Pool module itself. For example, the comparator has always a little offset, which can create either higher or lower result values. In addition, an overdrive error can occur out of the internal logic of the A-Pool. With a high A-Pool input frequency, the module might not react fast enough to stop the counter correctly.

example_adc_external_signal_slaa475.gifFigure 5. Example of ADC With External Signal and Counter Stop Logic