SLAA202B February   2005  – December 2018 MSP430F149 , MSP430F149 , MSP430F2252-Q1 , MSP430F2252-Q1 , MSP430F2272-Q1 , MSP430F2272-Q1 , MSP430F2274 , MSP430F2274 , MSP430FG4619 , MSP430FG4619

 

  1.   Implementing IrDA With MSP430™ MCUs
    1.     Trademarks
    2. 1 Introduction
    3. 2 Hardware Description
      1. 2.1 Hardware Overview
      2. 2.2 Circuit Description
    4. 3 Software Description
      1. 3.1 Implementing IrPHY Layer Using Timer_A
        1. 3.1.1 Transmission
        2. 3.1.2 Reception
      2. 3.2 Implementing IrPHY Layer using USCI_A0
      3. 3.3 Implementing IrLAP
        1. 3.3.1 Discovery Services
        2. 3.3.2 Connect Services
        3. 3.3.3 Data Services
        4. 3.3.4 Disconnect Services
      4. 3.4 Implementing IrLMP
        1. 3.4.1 Discovery Services
        2. 3.4.2 Link Connect and Connect Services
        3. 3.4.3 Data Services
        4. 3.4.4 Disconnect Services
      5. 3.5 IAS Implementation
      6. 3.6 TTP Implementation
      7. 3.7 IrCOMM Implementation
      8. 3.8 Application Layer
    5. 4 PC Demonstration Application
    6. 5 IrDA Protocol Basics
      1. 5.1 Physical (IrPHY) Layer
      2. 5.2 Link Access Protocol (IrLAP) Layer
      3. 5.3 Link Management Protocol (IrLMP) Layer
      4. 5.4 Information Access Services (IAS)
      5. 5.5 Tiny Transfer Protocol (TTP)
      6. 5.6 IrCOMM
    7. 6 IrDA Communication Diagram
    8. 7 Frame Exchange Log
    9. 8 References
  2.   Revision History

3.2 Implementing IrPHY Layer using USCI_A0

On MSP430 devices with a USCI peripheral module, the USCI_A0 can be used in UART mode to conveniently decode and encode the IrDA PHY pulse train. To activate the hardware bit shaping, the bit UCIREN in the UCA0IRCTL control register needs to be set.

The provided MSP430FG4619 and the MSP430F2274 demo applications operate with an SMCLK frequency of 4 MHz and use the exact same USCI initialization sequence. To achieve an IrDA baud rate of 9600 bps using a BRCLK frequency of 4 MHz with the oversampling mode enabled (UCOS16 = 1), the BITCLK16 frequency must be 9600 bps × 16 = 153.6 kHz. For this, the baud rate prescaler is set to 26, and a first-stage modulator setting of 1 is used, giving a very close match to the desired divider.

The IrDA transmitter is configured to generate pulses with a pulse length of exactly 3/16th of a bit time by setting UCIRTXCLK = 1 and UCITXPLx = 5. This setting can be reduced if a shorter pulse length is permissible, resulting in current savings during the operation of the externally connected IrDA transceiver. The byte transmission in IrDA mode is exactly the same as in UART mode. The application ensures that the transmit buffer can be loaded by ensuring that UCA0TXIFG is clear, and then simply loads the transmit data byte into UCA0TXBUF. The USCI module will then start transmitting and bit-shaping the IrDA pulse train.

The receiver configuration includes the setting of UCIRRXPL to match the polarity of the receive signal provided by the IrDA transceiver. An optional analog deglitch filter can be configured to improve system robustness; however, this feature is not used here. To receive data, the USCI_A0 receive interrupt is enabled, and the low-power mode is entered. Upon the reception of a data byte, the receive interrupt service routine is entered, and the data is fetched from the UCA0RXBUF receive buffer.

For more information on the configuration and operation of the USCI module, see the MSP430F4xx or MSP430F2xx family user's guides [12][13].