SBOK044B December   2020  – December 2024 TPS7H4010-SEP

 

  1.   1
  2. 1 Abstract
  3.   Trademarks
  4. 2 Introduction
  5. 3 Single-Event Effects (SEE)
  6. 4 Device and Test Board Information
  7. 5 Irradiation Facility and Setup
  8. 6 Depth, Range, and LETEFF Calculation
  9. 7 Test Setup and Procedures
  10. 8 Destructive Single-Event Effects (DSEE)
    1. 8.1 Single-Event Latch-up (SEL) Results
    2. 8.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 9 Single-Event Transients (SET)
  12. 10Event Rate Calculations
  13. 11Summary
  14. 12Revision History
  15.   A Total Ionizing Dose from SEE Experiments
  16.   B References

4 Device and Test Board Information

The TPS7H4010-SEP is packaged in a 30-pin WQFN plastic package as shown in Figure 4-1. The TPS7H4010EVM evaluation board was used to evaluate the performance and characteristics of the TPS7H4010-SEP under heavy-ions. Figure 4-2 shows the top view of the evaluation board used for the radiation testing. Figure 4-3 and Figure 4-4 shows the EVM board schematics for the VOUT = 3.3 V and VOUT = 1.8 V used for the heavy-ion testing campaign. See the TPS7H4010-SP Evaluation Module user's guide for more information about the evaluation board.

The package was delidded to reveal the die face for all heavy-ion testing.
TPS7H4010-SEP Photograph of Delidded TPS7H4010-SEP [Left] and Pinout Diagram [Right]Figure 4-1 Photograph of Delidded TPS7H4010-SEP [Left] and Pinout Diagram [Right]
TPS7H4010-SEP TPS7H4010-SEP Board Top ViewFigure 4-2 TPS7H4010-SEP Board Top View
TPS7H4010-SEP TPS7H4010EVM Schematic for VOUT = 3.3 VFigure 4-3 TPS7H4010EVM Schematic for VOUT = 3.3 V
TPS7H4010-SEP TPS7H4010EVM Schematic for VOUT = 1.8 VFigure 4-4 TPS7H4010EVM Schematic for VOUT = 1.8 V