6 Depth, Range, and LET_EFF Calculation

The TPS7H4010-SEP is fabricated in the TI Linear BiCMOS 180-nm process with a back-end-of-line (BEOL) stack consisting of 4 levels of standard thickness aluminum metal on a 0.6-μm pitch. The total stack height from the surface of the passivation to the silicon surface is 5.46 μm based on nominal layer thickness as shown in Figure 6-1. Accounting for energy loss through the 1-mil thick Aramica beam port window, the 40-mm air gap, and the BEOL stack over the TPS7H4010-SEP, the effective LET (LET_EFF) at the surface of the silicon substrate, the depth, and the ion range was determined with the SEUSS 2020 Software (provided by the Texas A&M Cyclotron Institute and based on the latest SRIM-2013 [7] models). The results are shown in Table 6-1. The LET_EFF vs range for the ⁸⁴Kr heavy-ion is shown on Figure 6-2. The stack was modeled as a homogeneous layer of silicon dioxide (valid since SiO₂ and aluminum density are similar).