SBAU352 June   2020 ADS131B04-Q1

 

  1.   ADS131B04-Q1 Evaluation Module
    1.     Trademarks
    2. 1 EVM Overview
      1. 1.1 ADS131B04-Q1EVM Kit
      2. 1.2 ADS131B04-Q1EVM Board
    3. 2 EVM Analog Interface
      1. 2.1 ADC Analog Input Signal Path
      2. 2.2 ADC External Clock (CLKIN) Options
    4. 3 Digital Interface
      1. 3.1 SPI Communication
      2. 3.2 Connection to the PHI
      3. 3.3 Digital Header
      4. 3.4 LaunchPad Connectors
    5. 4 Power Supplies
    6. 5 ADS131B04-Q1EVM Initial Setup
      1. 5.1 Default Jumper Settings
      2. 5.2 EVM Graphical User Interface (GUI) Software Installation
    7. 6 ADS131B04-Q1EVM Operation
      1. 6.1 EVM GUI Global Settings for ADC Control
      2. 6.2 Register Map Configuration Tool
      3. 6.3 Time Domain Display Tool
      4. 6.4 Spectral Analysis Tool
      5. 6.5 Histogram Tool
    8. 7 ADS131B04-Q1EVM Bill of Materials, PCB Layout, and Schematic
      1. 7.1 Bill of Materials
      2. 7.2 PCB Layout
      3. 7.3 Schematic

3.1 SPI Communication

The ADS131B04-Q1EVM supports limited interface modes as detailed in the ADS131B04-Q1 data sheet. The ADS131B04-Q1 uses an SPI-compatible interface to configure the device and retrieve conversion data. SPI communication on the ADS131B04-Q1 is performed in frames. Each SPI communication frame consists of several words. The word size is configurable as either 16 bits, 24 bits (default), or 32 bits by programming the WLENGTH[1:0] bits in the MODE register.

Additionally, the DRDY pin indicates when conversion data are available to be read by the master. The DRDY_SEL[1:0] bits, DRDY_HIZ bit, and the DRDY_FMT bit in the MODE register control the behavior of the DRDY pin.

For this EVM not all modes and functions for this SPI communication are supported. Functions not supported are disabled in the EVM GUI software. For more information about the SPI communication, see the ADS131B04-Q1 data sheet.