SBAU352 June   2020 ADS131B04-Q1

 

  1.   ADS131B04-Q1 Evaluation Module
    1.     Trademarks
    2. 1 EVM Overview
      1. 1.1 ADS131B04-Q1EVM Kit
      2. 1.2 ADS131B04-Q1EVM Board
    3. 2 EVM Analog Interface
      1. 2.1 ADC Analog Input Signal Path
      2. 2.2 ADC External Clock (CLKIN) Options
    4. 3 Digital Interface
      1. 3.1 SPI Communication
      2. 3.2 Connection to the PHI
      3. 3.3 Digital Header
      4. 3.4 LaunchPad Connectors
    5. 4 Power Supplies
    6. 5 ADS131B04-Q1EVM Initial Setup
      1. 5.1 Default Jumper Settings
      2. 5.2 EVM Graphical User Interface (GUI) Software Installation
    7. 6 ADS131B04-Q1EVM Operation
      1. 6.1 EVM GUI Global Settings for ADC Control
      2. 6.2 Register Map Configuration Tool
      3. 6.3 Time Domain Display Tool
      4. 6.4 Spectral Analysis Tool
      5. 6.5 Histogram Tool
    8. 7 ADS131B04-Q1EVM Bill of Materials, PCB Layout, and Schematic
      1. 7.1 Bill of Materials
      2. 7.2 PCB Layout
      3. 7.3 Schematic

4 Power Supplies

The PHI provides multiple power-supply options for the EVM, derived from the USB supply of the computer.

The EEPROM on the ADS131B04-Q1EVM uses a 3.3-V power supply generated directly by the PHI. The analog supply of the ADC is powered by the LP5907 onboard the EVM, which is a low-noise linear regulator that uses the 5-V supply on the PHI to generate a cleaner 3.3-V output. The 3.3-V supply to the digital section of the ADC is provided directly by an LDO on the PHI.

The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where possible, between bypass capacitors and their loads to minimize inductance along the load current path.

As mentioned previously in Section 1, power to the EVM is supplied by the PHI through connector J5. For information about PHI pins and the power connections, see Table 5.

With modifications, the user may use external supplies for either AVDD or DVDD. AVDD can be driven externally by moving the jumper on JP9 to the left. This placement disconnects 3V3_LDO from AVDD. Power can then be applied through the AVDD test point at TP2 or through 3V3_LP if connector J8 is installed. DVDD can be driven externally from the DVDD test point at TP1 if R45 is removed from the EVM.