SBAK047 March   2025 ADC3664-SEP

 

  1.   1
  2.   2
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects
  6. 3Irradiation Facility and Setup
  7. 4Depth, Range, and LETEFF Calculation
  8. 5Test Setup and Procedures
  9. 6Destructive Single-Event Effects (DSEE)
    1. 6.1 Single-Event Latch-Up (SEL) Results
  10. 7Single-Event Transients (SET)
    1. 7.1 Single Event Transients
  11. 8Summary
  12. 9References

1 Introduction

The ADC3664-SEP is a low latency, low noise, and ultra low power, 14-bit, 125MSPS, high-speed dual channel ADC. Designed for best noise performance, the device delivers a noise spectral density of – 156.9dBFS/Hz combined with excellent linearity and dynamic range. The ADC3664-SEP offers DC precision together with IF sampling support to enable the design of a wide range of applications. The low latency architecture (as low as 1 clock cycle latency) and high sample rate also enable high speed control loops. The ADC consumes only 100mW/ch at 125MSPS and the power consumption scales well with sampling rate.

The device uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device also integrates a digital down converter (DDC) to help reduce the data rate and lower system power consumption. The ADC3664-SEP is pinto-pin compatible with a family of 16-bit resolution ADCs.

Table 1-1 Overview Information
Description (1)Device Information
Generic Part NumberADC3664-SEP
Orderable Part NumberADC3664-SEP
Device FunctionLow-Noise Dual 14-Bit 125MSPS ADC
Device Package40-pin VQFN RSB (5 × 5mm)
TechnologyTI C021 65nm CMOS
Exposure FacilityRadiation Effects Facility Cyclotron Institute, Texas A&M University (15MeV / Nucleon)
Heavy Ion Fluence per runUp to 1 × 107 ions/cm2
Irradiation Temperature25°C (for SET testing) and 125°C (for SEL testing)
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