SBAA520A July   2021  – December 2025 ADS117L11 , ADS127L11 , ADS127L14 , ADS127L18 , ADS127L21 , ADS127L21B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Clock Signal
    1. 2.1 Single Clock Buffer
    2. 2.2 Multiple Clock Buffers
    3. 2.3 Clock Jitter
  6. 3 Synchronization
  7. 4 Anti-Alias Filter Group Delay
  8. 5 Reference Voltage
  9. 6 Power Supply Bypassing and Grounding
  10. 7 SPI Daisy-Chain Connection
    1. 7.1 SPI Daisy-Chain Communication
    2. 7.2 System Requirements for SPI Daisy-Chain Configuration
    3. 7.3 Number of Devices in a SPI Daisy-Chain Connection for Single Channel ADCs
  11. 8 Parallel SPI SDO or DRDY Connection for Single Channel ADCs
  12. 9 Determining When New Conversion Data is Available for Single Channel ADCs
  13. 10Frame-Sync Daisy-Chain Connection for Multi-Channel ADCs
    1. 10.1 System Requirements for Frame-Sync Daisy-Chain Configuration
    2. 10.2 Number of Channels in a Frame-Sync Daisy-Chain Connection
  14. 11Summary
  15. 12References
  16. 13Revision History

10.1 System Requirements for Frame-Sync Daisy-Chain Configuration

There are several requirements when the multichannel ADCs are configured in daisy-chain. These requirements are specific to the ADS117L14, ADS117L18, ADS127L14, and ADS127L18 devices. All register settings not specified in the following steps are default reset values.

Register Configuration Settings:

  1. DP_DAISY = 0b in the DP_CFG1 register. (Default setting for SPI and Hardware Programming Mode)
  2. CLK and DCLK dividers must be programmed to the divide by 1 option. CLK_DIV[2:0] = 000b in the CLK_CFG register and DCLK_DIV[1:0] = 00b in the DP_CFG2 register. (Default settings for SPI and Hardware Programming Mode)
  3. Set CLK_SEL = 1b in the CLK_CFG register. External clock operation is required for frame-sync daisy-chain operation. Hardware Programming Mode uses External Clock by default. SPI Programming uses Internal Clock by default such that the user must set the CLK_SEL bit to 1.
  4. DP_TDM[1:0] (TDM mode or number of data lanes) is programmed the same for all devices in the chain.
  5. Reduce the complexity of interfacing to the ADCs by programming each device for the same frame length with a parallel write operation. (Program individual frame length as 16, 24, 32, or 40 bits for all devices)

Hardware Configuration Settings:

  1. The devices are synchronized together using the START pin.
  2. The START pin rising edge must meet the setup and hold timing requirements relative to CLK specified in the timing requirements section of the data sheet. If not met, then frame-sync daisy-chain data is corrupted.
  3. Use 100kΩ pull-down resistors on unused DOUT2 and DOUT3 pins. Leave DOUT1 floating if unused. Connect unused DIN pins to GND or IOVDD.
  4. All digital signals for the multichannel ADCs support 1.8V logic levels only. These devices are damaged by voltages greater than 2.2V.

Figure 10-8 shows an example of two multichannel ADCs in daisy-chain configuration using SPI Programming Mode. This configuration can be further expanded to include more than two multichannel ADCs.

ADS127L11 ADS117L11 ADS127L21 ADS127L18 ADS127L14 ADS127L21B Frame-Sync Daisy-Chain with SPI Programming Mode Figure 10-8 Frame-Sync Daisy-Chain with SPI Programming Mode

Notes:

  1. START signal must meet setup and hold time relative to CLKIN rising edge.
  2. If RESET is not connected to controller, then connect to IOVDD.
  3. If ERROR pin is used, connect 100kΩ pull-up to IOVDD.
  4. If DP_TDM[1:0] = 00b or 01b, connect 100kΩ pulldown resistors from DOUT2 and DOUT3 to GND.
  5. Unused DIN0, DIN1, DIN2, and DIN3 pins must be connected to GND or IOVDD.
  6. DOUT1 is always an output and must be left floating if not used.