SBAA520A July   2021  – December 2025 ADS117L11 , ADS127L11 , ADS127L14 , ADS127L18 , ADS127L21 , ADS127L21B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Clock Signal
    1. 2.1 Single Clock Buffer
    2. 2.2 Multiple Clock Buffers
    3. 2.3 Clock Jitter
  6. 3 Synchronization
  7. 4 Anti-Alias Filter Group Delay
  8. 5 Reference Voltage
  9. 6 Power Supply Bypassing and Grounding
  10. 7 SPI Daisy-Chain Connection
    1. 7.1 SPI Daisy-Chain Communication
    2. 7.2 System Requirements for SPI Daisy-Chain Configuration
    3. 7.3 Number of Devices in a SPI Daisy-Chain Connection for Single Channel ADCs
  11. 8 Parallel SPI SDO or DRDY Connection for Single Channel ADCs
  12. 9 Determining When New Conversion Data is Available for Single Channel ADCs
  13. 10Frame-Sync Daisy-Chain Connection for Multi-Channel ADCs
    1. 10.1 System Requirements for Frame-Sync Daisy-Chain Configuration
    2. 10.2 Number of Channels in a Frame-Sync Daisy-Chain Connection
  14. 11Summary
  15. 12References
  16. 13Revision History

13 Revision History

Changes from Revision * (July 2021) to Revision A (December 2025)

  • Updated to include multichannel ADCsGo
  • Added frame-sync data port in daisy-chain applicationsGo
  • Updated format to a full application noteGo
  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Updated the title of the documentGo
  • Added new reference and corrected existing reference.Go