Daisy-chain operation for the ADS1x7Lxx family requires no special programming. The user configures the host controller to extend the data frame to the length needed to access the data from all ADCs connected in the chain. The new data frame length is set to match the number of devices in a chain multiplied by the number of bits per frame of the ADC. For example, four devices in a chain using 24b ADC data packets require the user to set the controller frame length to ninety-six bits.

When shifting data into the daisy-chain, the first block of data is targeted for the last device in the chain connection (ADC 4 in Figure 7-3). The ADCs only interpret the data in the respective shift registers when CS is taken high. This means there is no limit to the amount of shift operations as the data passes through each ADC, only the last bits shifted into each ADC matter. Figure 7-4 shows an example of 24b input data packets per each ADC to match the 24b output data size. See the ADS1x7Lxx family data sheets for additional details regarding the daisy-chain input command format.

Figure 7-4 SPI Daisy-Chain Data Input Sequence

When reading data from the ADC, the first data output on SDO/DRDY is from the last device in the chain (ADC 4 in Figure 7-3), followed by data from the next device in the chain (ADC 3), and so on (see Figure 7-5). There is no interruption or gap in the data stream between devices. For example, if the ADCs are programmed for 24b SPI data packets, perform ninety-six shift operations to read data from four devices.

Figure 7-5 SPI Daisy-Chain Data Output Sequence

Reading register data requires two frames. The first frame inputs the read register command with the general format shown in Figure 7-4. The second frame outputs the register data, with the general format shown in Figure 7-5. The first register output data is from device #4 with two additional bytes inserted after the register data byte. The additional bytes fill out the individual ADC frames to equal the 24b data size. Even though the total number of register data bytes is four (one byte from each ADC), ninety-six shift operations are needed to read the register data from all the ADCs. The additional bytes can be 00h pad bytes, or other values depending on the specific ADC and configuration. See the ADS1x7Lxx data sheet for details on the exact contents of the returned data. Figure 7-6 is an example of a 4 ADC daisy-chain read register data, with 24b frame size per ADC.

A. Depending on the previous operation, the data field is either conversion data or register data + two 00h pad bytes.

B. Previous state of SDO/DRDY before the first SCLK.

Figure 7-6 Daisy-Chain Read Register Data