SBAA520A July   2021  – December 2025 ADS117L11 , ADS127L11 , ADS127L14 , ADS127L18 , ADS127L21 , ADS127L21B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Clock Signal
    1. 2.1 Single Clock Buffer
    2. 2.2 Multiple Clock Buffers
    3. 2.3 Clock Jitter
  6. 3 Synchronization
  7. 4 Anti-Alias Filter Group Delay
  8. 5 Reference Voltage
  9. 6 Power Supply Bypassing and Grounding
  10. 7 SPI Daisy-Chain Connection
    1. 7.1 SPI Daisy-Chain Communication
    2. 7.2 System Requirements for SPI Daisy-Chain Configuration
    3. 7.3 Number of Devices in a SPI Daisy-Chain Connection for Single Channel ADCs
  11. 8 Parallel SPI SDO or DRDY Connection for Single Channel ADCs
  12. 9 Determining When New Conversion Data is Available for Single Channel ADCs
  13. 10Frame-Sync Daisy-Chain Connection for Multi-Channel ADCs
    1. 10.1 System Requirements for Frame-Sync Daisy-Chain Configuration
    2. 10.2 Number of Channels in a Frame-Sync Daisy-Chain Connection
  14. 11Summary
  15. 12References
  16. 13Revision History

7.2 System Requirements for SPI Daisy-Chain Configuration

There are several requirements when the ADCs are configured in a daisy-chain:

  1. Use the four-wire SPI mode and one CS control line to simultaneously select and deselect the ADCs in the chain.
  2. For single-channel devices the SDO/DRDY pin must be programmed in the data-output only mode. Do not use the SDO/DRDY dual function mode with daisy-chain operation.
    1. The ADS117L11 and ADS127L11 ADCs default to the data-output only mode after reset and can be used in a daisy-chain configuration without additional register setting changes.
    2. The ADS127L21 and ADS127L21B default to dual SDO/DRDY mode after reset and must be reconfigured to data-output only mode by writing 00b to the DATA_MODE field in the FILTER3 register. For the following procedure, refer to Figure 7-3.
      1. First, program ADC1 SDO/DRDY to data-output only mode using a register write frame.
      2. Once ADC1 is programmed correctly, ADC2 can then be programmed in the next register write frame.
      3. Continue this procedure until all ADCs in the daisy-chain have been programmed to data-output only mode.
      4. Note that each ADC in the daisy chain requires a separate write register frame, or 4 register write frames for 4 ADCs.
  3. To reduce the complexity of interfacing to the ADCs, program the ADCs to the same data packet length using a parallel write operation. Program individual data packets as 16, 24 32, or 40 bits for single channel devices or 16 or 24 bits for multichannel devices.
  4. Install pull-up resistors between the combined SDI-SDO connections and IOVDD. These resistors prevent the SDI inputs from floating in any condition because CS tri-states SDO.