In systems with a small number of channels, a single clock buffer can be used to drive all ADCs. This is possible due to the small dimensions of the ADS1x7Lxx ADC, allowing for a small board layout resulting in short PCB trace lengths between the ADCs and the clock source. In a single-clock buffer layout, the PCB traces from the clock buffer to the ADCs must have equal path lengths to minimize sampling skew between the ADCs. Given the typical propagation delay of a micro-strip PCB design is 60ps/cm, a five-cm difference between the clock traces results in 300ps sampling skew between ADCs. This sampling skew appears as an additional 0.3ns of group delay in the input signal and must be included in the measurement error budget when phase angle between channels is important.

In addition to sampling skew, matched PCB trace lengths also reduce multiple line reflections from the ADC clock inputs. Multiple line reflections can lead to excessive ringing and overshoot, therefore reducing the clock signal noise margin.

Figure 2-1 shows an example of matched clock trace lengths. TI recommends this configuration for trace lengths of 5cm or less, and up to four ADCs. Using longer PCB traces or more ADCs result in excessive clock rise and fall times, reducing the clock signal noise margin.

Figure 2-1 Single Clock Buffer