SBAA520A July   2021  – December 2025 ADS117L11 , ADS127L11 , ADS127L14 , ADS127L18 , ADS127L21 , ADS127L21B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Clock Signal
    1. 2.1 Single Clock Buffer
    2. 2.2 Multiple Clock Buffers
    3. 2.3 Clock Jitter
  6. 3 Synchronization
  7. 4 Anti-Alias Filter Group Delay
  8. 5 Reference Voltage
  9. 6 Power Supply Bypassing and Grounding
  10. 7 SPI Daisy-Chain Connection
    1. 7.1 SPI Daisy-Chain Communication
    2. 7.2 System Requirements for SPI Daisy-Chain Configuration
    3. 7.3 Number of Devices in a SPI Daisy-Chain Connection for Single Channel ADCs
  11. 8 Parallel SPI SDO or DRDY Connection for Single Channel ADCs
  12. 9 Determining When New Conversion Data is Available for Single Channel ADCs
  13. 10Frame-Sync Daisy-Chain Connection for Multi-Channel ADCs
    1. 10.1 System Requirements for Frame-Sync Daisy-Chain Configuration
    2. 10.2 Number of Channels in a Frame-Sync Daisy-Chain Connection
  14. 11Summary
  15. 12References
  16. 13Revision History

7.3 Number of Devices in a SPI Daisy-Chain Connection for Single Channel ADCs

The following section is only applicable to single-channel devices. For multichannel devices, refer to Number of Channels in a Frame-Sync Daisy-Chain Connection.

The maximum number of single channel devices connected in a chain is limited by the SPI clock speed, the length of the ADC data frame, and the ADC data rate. In other words, the SPI clock speed must be fast enough to read data from all devices in one conversion cycle or data is lost. This requirement is also true using the standard SPI cascade connection because data is also read sequentially in this mode.

The single channel ADS1x7Lxx devices support SCLK speeds up to 50MHz. However, achieving 50MHz operation requires a non-standard SPI timing configuration, where data is clocked out and clocked in on the same clock edge. This non-standard SPI timing configuration is not supported in daisy-chain mode. Using standard opposite edge clock-out and clock-in SPI operation, and accounting for SPI propagation delay and setup time, the SCLK speed is limited to approximately 16.5MHz in a daisy-chain configuration. Operating IOVDD at 2V or greater (only possible with the single channel ADCs) reduces the propagation delay time, increasing the maximum SCLK speed to approximately 20MHz.

Equation 2 shows that the number of ADCs connected in a single daisy-chain is determined by the SCLK frequency, the data rate, and the bits per frame of each ADC.

Equation 2. M a x i m u m   n u m b e r   o f   d e v i c e s   i n   a   d a i s y ‐ c h a i n   c o n n e c t i o n =   f S C L K f D A T A   × b i t s   p e r   f r a m e

For example, if fSCLK = 20MHz, fDATA = 100kSPS and the ADC outputs 24 bits per frame, the number of devices in a single daisy-chain is limited to the floor of: 20MHz / (100kHz × 24) = 8.

If the maximum number of devices is less than desired according to Equation 2, the number of devices can be increased by using another daisy-chain with a separate data output line (SDO/DRDY). The two data output lines enable parallel output-data shift operations from the two daisy-chains. CS, DIN and SCLK lines can be shared between the daisy-chains to keep the number of SPI lines at a minimum. Figure 7-7 illustrates this configuration.

ADS127L11 ADS117L11 ADS127L21 ADS127L18 ADS127L14 ADS127L21B Daisy-Chain SPI Connection with 2 Parallel Output Figure 7-7 Daisy-Chain SPI Connection with 2 Parallel Output