ZHCS429J March   2012  – November 2021 UCD3138

PRODUCTION DATA  

  1. 特性
  2. 应用范围
  3. 说明
  4. 功能方框图
  5. Revision History
  6. Device Comparison Table
    1. 6.1 Product Family Comparison
    2. 6.2 Product Selection Matrix
  7. Pin Configuration and Functions
    1. 7.1 UCD3138RGC 64 QFN Pin Attributes
    2. 7.2 UCD3138RHA, UCD3138RMH and UCD3138RJA Pin Attributes
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing and Switching Characteristics
    7. 8.7 Power Supply Sequencing
    8. 8.8 Peripherals
      1. 8.8.1 Digital Power Peripherals (DPPs)
        1. 8.8.1.1 Front End
        2. 8.8.1.2 DPWM Module
        3. 8.8.1.3 DPWM Events
        4. 8.8.1.4 High Resolution DPWM
        5. 8.8.1.5 Oversampling
        6. 8.8.1.6 DPWM Interrupt Generation
        7. 8.8.1.7 DPWM Interrupt Scaling/Range
    9. 8.9 Typical Temperature Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 ARM Processor
    3. 9.3 Memory
      1. 9.3.1 CPU Memory Map and Interrupts
      2. 9.3.2 Boot ROM
      3. 9.3.3 Customer Boot Program
      4. 9.3.4 Flash Management
    4. 9.4 System Module
      1. 9.4.1 Address Decoder (DEC)
      2. 9.4.2 Memory Management Controller (MMC)
      3. 9.4.3 System Management (SYS)
      4. 9.4.4 Central Interrupt Module (CIM)
    5. 9.5 Feature Description
      1. 9.5.1  Sync FET Ramp and IDE Calculation
      2. 9.5.2  Automatic Mode Switching
        1. 9.5.2.1 Phase Shifted Full Bridge Example
        2. 9.5.2.2 LLC Example
        3. 9.5.2.3 Mechanism for Automatic Mode Switching
      3. 9.5.3  DPWMC, Edge Generation, IntraMux
      4. 9.5.4  Filter
        1. 9.5.4.1 Loop Multiplexer
        2. 9.5.4.2 Fault Multiplexer
      5. 9.5.5  Communication Ports
        1. 9.5.5.1 SCI (UART) Serial Communication Interface
        2. 9.5.5.2 PMBUS
        3. 9.5.5.3 General Purpose ADC12
        4. 9.5.5.4 Timers
          1. 9.5.5.4.1 24-bit PWM Timer
          2. 9.5.5.4.2 16-Bit PWM Timers
          3. 9.5.5.4.3 Watchdog Timer
      6. 9.5.6  Miscellaneous Analog
      7. 9.5.7  Package ID Information
      8. 9.5.8  Brownout
      9. 9.5.9  Global I/O
      10. 9.5.10 Temperature Sensor Control
      11. 9.5.11 I/O Mux Control
      12. 9.5.12 Current Sharing Control
      13. 9.5.13 Temperature Reference
    6. 9.6 Device Functional Modes
      1. 9.6.1 Normal Mode
      2. 9.6.2 Phase Shifting
      3. 9.6.3 DPWM Multiple Output Mode
      4. 9.6.4 DPWM Resonant Mode
      5. 9.6.5 Triangular Mode
      6. 9.6.6 Leading Edge Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 10.2.2.2 DPWM Initialization for PSFB
        3. 10.2.2.3 DPWM Synchronization
        4. 10.2.2.4 Fixed Signals to Bridge
        5. 10.2.2.5 Dynamic Signals to Bridge
        6. 10.2.2.6 System Initialization for PCM
          1. 10.2.2.6.1 Use of Front Ends and Filters in PSFB
          2. 10.2.2.6.2 Peak Current Detection
          3. 10.2.2.6.3 Peak Current Mode (PCM)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Introduction To Power Supply and Layout Recommendations
    2. 11.2 3.3-V Supply Pins
    3. 11.3 Recommendation for V33 Ramp up Slew Rate for UCD3138 and UCD3138064
    4. 11.4 Recommendation for RC Time Constant of RESET Pin for UCD3138 and UCD3138064
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 EMI and EMC Mitigation Guidelines
      2. 12.1.2 BP18 Pin
      3. 12.1.3 Additional Bias Guidelines
      4. 12.1.4 UCD3138 Pin Connection Recommendation
        1. 12.1.4.1 Current Amplifier With EADC Connection
        2. 12.1.4.2 DPWM Synchronization
        3. 12.1.4.3 GPIOS
        4. 12.1.4.4 DPWM PINS
        5. 12.1.4.5 EAP and EAN Pins
        6. 12.1.4.6 ADC Pins
      5. 12.1.5 UART Communication Port
      6. 12.1.6 Special Considerations
    2. 12.2 Layout Example
      1. 12.2.1 UCD3138 and UCD3138064 40 Pin
      2. 12.2.2 UCD3138 and UCD3138064 64 Pin
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Code Composer Studio
      2. 13.1.2 Tools and Documentation
    2. 13.2 Documentation Support
      1. 13.2.1 References
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 术语表
  14. 14Mechanical Packaging and Orderable Information
    1. 14.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics

V33A = V33D = V33DIO = 3.3 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETERTEST CONDITIONMINTYPMAXUNIT
SUPPLY CURRENT
I33AMeasured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled6.3mA
I33DIOAll GPIO and communication pins are open0.35mA
I33DROM program execution60mA
I33DFlash programming in ROM mode70mA
I33The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded.100mA
ERROR ADC INPUTS EAP, EAN
EAP – AGND–0.151.998V
EAP – EAN–0.2561.848V
Typical error rangeAFE = 0–256248mV
EAP – EAN Error voltage digital resolutionAFE = 30.811.20mV
AFE = 21.722.30mV
AFE = 13.5544.45mV
AFE = 06.9089.10mV
REAInput impedance (See Figure 8-4)AGND reference0.5MΩ
IOFFSETInput offset current (See Figure 8-4)–55μA
EADC offsetInput voltage = 0 V at AFE = 0–22LSB
Input voltage = 0 V at AFE = 1–2.52.5LSB
Input voltage = 0 V at AFE = 2–3-3LSB
Input voltage = 0 V at AFE = 3–44LSB
Sample Rate16MHz
Analog Front End Amplifier Bandwidth100MHz
A0GainSee Figure 8-51V/V
Minimum output voltage100mV
EADC DAC
DAC range01.6V
VREF DAC reference resolution10 bit, No dithering enabled1.56mV
VREF DAC reference resolutionWith 4 bit dithering enabled97.6μV
INL–3.03.0LSB
DNLDoes not include MSB transition–2.11.6LSB
DNL at MSB transition–1.4LSB
DAC reference voltage1.581.61V
τSettling TimeFrom 10% to 90%250ns
ADC12
IBIASBias current for PMBus address pins9.510.5μA
Measurement range for voltage monitoring02.5V
Internal ADC reference voltage–40°C to 125°C2.4752.5002.525V
Change in Internal ADC reference from 25°C reference voltage(1)–40°C to 25°C–0.4mV
25°C to 85°C–1.8
25°C to 125°C–4.2
ADC12 INL integral nonlinearity(1)ADC_SAMPLINGSEL = 6 for all ADC12 data, 25 °C to 125 °C±2.5LSB
ADC12 DNL differential nonlinearity(1)–0.7/+2.5LSB
ADC Zero Scale Error–77mV
ADC Full Scale Error–3535mV
Input bias2.5 V applied to pin400nA
Input leakage resistance(1)ADC_SAMPLINGSEL= 6 or 01MΩ
Input Capacitance(1)10pF
ADC single sample conversion time(1)ADC_SAMPLINGSEL= 6 or 03.9μs
DIGITAL INPUTS/OUTPUTS(2)(3)
VOLLow-level output voltage(4)IOH = 4 mA, V33DIO = 3 VDGND
+ 0.25
V
VOHHigh-level output voltage (4)IOH = –4 mA, V33DIO = 3 VV33DIO – 0.6V
VIHHigh-level input voltageV33DIO = 3 V2.1V
VILLow-level input voltageV33DIO = 3 V1.1V
IOHOutput sinking current4mA
IOLOutput sourcing current–4mA
SYSTEM PERFORMANCE
TWDWatchdog time out rangeTotal time is: TWD × (WDCTRL.PERIOD + 1)14.61720.5ms
Time to disable DPWM output based on active FAULT pin signalHigh level on FAULT pin70ns
Processor master clock (MCLK)31.25MHz
tDelayDigital compensator delay(5)(1 clock = 32 ns)6clocks
t(reset)Pulse width needed at reset(1)10µs
Retention period of flash content (data retention and program)TJ = 25°C100years
Program time to erase one page or block in data flash or program flash20ms
Program time to write one word in data flash or program flash20µs
f(PCLK)Internal oscillator frequency240250260MHz
Sync-in/sync-out pulse widthSync pin256ns
Flash Read1MCLKs
Flash Write20μs
ISHARECurrent share current source (See Figure 9-16)238259μA
RSHARECurrent share resistor (See Figure 9-16)9.7510.3
POWER ON RESET AND BROWN OUT (V33D pin, See Figure 8-3)
VGHVoltage good high2.7V
VGLVoltage good low2.5V
VresVoltage at which IReset signal is valid0.8V
TPORTime delay after power is good or RESET* relinquished1ms
BrownoutInternal signal warning of brownout conditions2.9V
TEMPERATURE SENSOR(6)
VTEMPVoltage range of sensor1.462.44V
Voltage resolutionV/°C5.9mV/°C
Temperature resolution°C per bit0.1034°C/LSB
Accuracy(6)(7)–40°C to 125°C–10±510°C
Temperature range–40°C to 125°C–40125°C
ITEMPCurrent draw of sensor when active30μA
TONTurn on time / settling time of sensor100μs
VAMBAmbient temperatureTrimmed 25°C reading1.85V
ANALOG COMPARATOR
DACReference DAC Range02.5V
Reference Voltage2.4782.52.513V
Bits7bits
INL(6)–0.420.21LSB
DNL(6)0.060.12LSB
Offset–5.519.5mV
Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator.(1)150ns
Reference DAC buffered output load(8)0.51mA
Buffer offset (–0.5 mA)4.68.3mV
Buffer offset (1.0 mA)–0.0517mV
As designed and characterized. Not 100% tested in production.
DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
On the 40-pin package V33DIO is connected to V33D internally.
The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.
Characterized by design and not production tested.
Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
Available from reference DACs for comparators D, E, F, and G.