ZHCSRA0 数据表 | 德州仪器 TI.com.cn

ZHCSRA0 December 2022 UCC5871-Q1

PRODUCTION DATA

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机械数据 (封装 | 引脚)

DWJ|36
- MPSS110A

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsra0_oa

6.9 SPI Timing Requirements

		MIN	NOM	MAX	UNIT
f_SPI	SPI clock frequency⁽¹⁾			4	MHz
t_CLK	SPI clock period⁽¹⁾	250			ns
t_CLKH	CLK logic high duration⁽¹⁾	90			ns
t_CLKL	CLK logic low duration⁽¹⁾	90			ns
t_{SU_NCS}	time between falling edge of nCS and rising edge of CLK⁽¹⁾	50			ns
t_{SU_SDI}	setup time of SDI before the falling edge of CLK⁽¹⁾	30			ns
t_{HD_SDI}	SDI data hold time ⁽¹⁾	45			ns
t_{D_SDO}	time delay from rising edge of CLK to data valid at SDO(2)			60	ns
t_{HD_SDO}	SDO output hold time⁽¹⁾	40			ns
t_{HD_NCS}	time between the falling edge of CLK and rising edge of nCS⁽¹⁾	50			ns
t_{HI_NCS}	SPI transfer inactive time⁽¹⁾	250			ns
t_ACC	nCS low to SDO out of high impedance(2)		60	80	ns
t_DIS	time between rising edge of nCS and SDO in tri-state(2)		30	50	ns

(1) Ensured by bench characterization.