ZHCS779B March   2012  – December 2023 UCC28070A

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Voltage Biasing (VCC and VVREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio and Sense Resistor (RS))
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Current-Loop Feedback Configuration
(Sizing of the Current-Transformer Turns-Ratio and Sense Resistor (RS))

A current-sense transformer (CT) is typically used in high-power applications to sense inductor current and avoid the losses inherent in the use of a current-sensing resistor. For average current-mode control, the entire inductor current waveform is required; however low-frequency CTs are obviously impracticable. Normally, two high-frequency CTs are used, one in the switching leg to obtain the up-slope current and one in the diode leg to obtain the down-slope current. These two current signals are summed together to form the entire inductor current, but this is not necessary with the UCC28070A.

A major advantage of the UCC28070A design is the current-synthesis function, which internally recreates the inductor current down-slope during the switching period OFF-time. This eliminates the need for the diode-leg CT in each phase, significantly reducing space, cost and complexity. A single resistor programs the synthesizer down slope, as previously discussed in the Current Synthesizer section.

A number of trade-offs must be made in the selection of the CT. Various internal and external factors influence the size, cost, performance, and distortion contribution of the CT.

These factors include, but are not limited to:

  • Turns-ratio (NCT)
  • Magnetizing inductance (LM)
  • Leakage inductance (LLK)
  • Volt-microsecond product (Vμs)
  • Distributed capacitance (Cd)
  • Series resistance (RSER)
  • External diode drop (VD)
  • External current sense resistor (RS)
  • External reset network

Traditionally, the turns-ratio and the current sense resistor are selected first. Some iterations may be needed to refine the selection once the other considerations are included.

In general, 50 ≤ NCT ≤ 200 is a reasonable range from which to choose. If NCT is too low, there may be high power loss in RS and insufficient LM. If too high, there could be excessive LLK and Cd. (A one-turn primary winding is assumed.)

GUID-F4F543D3-B45A-4201-96F9-88D64026DB1E-low.gifFigure 7-2 Current Sense Transformer Equivalent Circuit

A major contributor to distortion of the input current is the effect of magnetizing current on the CT output signal (iRS). A higher turns-ratio results in a higher LM for a given core size. LM must be high enough that the magnetizing current (iM) generated is a very small percentage of the total transformed current. This is an impossible criterion to maintain over the entire current range, because iM unavoidably becomes a larger fraction of iRS as the input current decreases toward zero. The effect of iM is to steal some of the signal current away from RS, reducing the CSx voltage and effectively understating the actual current being sensed. At low currents, this understatement can be significant and CAOx increases the current-loop duty-cycle in an attempt to correct the CSx input(s) to match the IMO reference voltage. This unwanted correction results in overstated current on the input wave shape in the regions where the CT understatement is significant, such as near the AC line zero crossings. It can affect the entire waveform to some degree under the high line, light-load conditions.

The sense resistor RS is chosen, in conjunction with NCT, to establish the sense voltage at CSx to be about 3V at the center of the reflected inductor ripple current under maximum load. The goal is to maximize the average signal within the common-mode input range VCMCAO of the CAOx current-error amplifiers, while leaving room for the peaks of the ripple current within VCMCAO. The design condition must be at the lowest maximum input power limit as determined in Linear Multiplier and Quantized Voltage Feed Forward. If the inductor ripple current is so high as to cause VCSx to exceed VCMCAO, then RS or NCT or both must be adjusted to reduce peak VCSx, which could reduce the average sense voltage center below 3V. There is nothing wrong with this situation; but be aware that the signal is more compressed between full-load and no-load, with potentially greater distortion at light loads.

The matter of volt-second balancing is important, especially with the widely varying duty-cycles in the PFC stage. Ideally, the CT is reset once each switching period; that is, the OFF-time Vμs product equals the ON-time Vμs product. ON-time Vμs is the time-integral of the voltage across LM generated by the series elements RSER, LLK, D, and RS. Off-time Vμs is the time-integral of the voltage across the reset network during the OFF-time. With passive reset, Vμs(off) is unlikely to exceed Vμs(on). Sustained unbalance in the on or off Vμs products leads to core saturation and a total loss of the current-sense signal. Loss of VCSx causes VCAOx to quickly rise to its maximum, programming a maximum duty-cycle at any line condition. This, in turn causes the boost inductor current to increase without control, until the system fuse or some component failure interrupts the input current.

It is vital that the CT has plenty of Vμs design-margin to accommodate various special situations where there may be several consecutive maximum duty-cycle periods at maximum input current, such as during peak current limiting.

Maximum Vμs(on) can be estimated by:

Equation 51. Vμs(on)max=VRS+VD+VRSER+VLK×tON(max)

where

  • all factors are maximized to account for worst-case transient conditions
  • tON(max) occurs during the lowest dither frequency, if frequency dithering is enabled

For design margin, a CT rating of approximately 5 × Vμs(on)max or higher is suggested. The contribution of VRS varies directly with the line current. However, VD may have a significant voltage even at near-zero current, so substantial Vμs(on) may accrue at the zero-crossings where the duty-cycle is maximum. VRSER is the least contributor, and often can be neglected if RSER < RS. VLK is developed by the di/dt of the sensed current, and is not observable externally. However, its impact is considerable, given the sub-microsecond rise-time of the current signal plus the slope of the inductor current. Fortunately, most of the built-up Vμs across LM during the ON-time is removed during the fall-time at the end of the duty-cycle, leaving a lower net Vμs(on) to be reset during the OFF-time. Nevertheless, the CT must, at the very minimum, be capable of sustaining the full internal Vμs(on)max built up until the moment of turn-off within a switching period.

To reset the CT, Vμs(off) may be generated with a resistor or Zener diode, using the iM as bias current.

GUID-0137AD5F-5E3E-4A29-844A-BBF8F58BBE10-low.gifFigure 7-3 Possible Reset Networks

To accommodate various CT circuit designs and prevent the potentially destructive result due to CT saturation, the UCC28070A maximum duty-cycle must be programmed such that the resulting minimum OFF-time accomplishes the required worst-case reset. (See Programming the PWM Frequency and Maximum Duty-Cycle Clamp for more information on sizing RDMX.) Be aware that excessive Cd in the CT can interfere with effective resetting, because the maximum reset voltage is not reached until after 1/4-period of the CT self-resonant frequency. A higher turns-ratio results in higher Cd [6], so a trade-off between NCT and DMAX must be made.

The selected turns-ratio also affects LM and LLK, which vary proportionally to the square of the turns. Higher LM is good, while higher LLK is not. If the voltage across LM during the ON-time is assumed to be constant (which it is not, but close enough to simplify) then the magnetizing current is an increasing ramp.

This upward ramping current subtracts from iRS, which affects VCSx especially heavily at the zero-crossings and light loads, as stated earlier. With a reduced peak at VCSx, the current synthesizer starts the down-slope at a lower voltage, further reducing the average signal to CAOx and further increasing the distortion under these conditions. If low input current distortion at very light loads is required, special mitigation methods may need to be developed to accomplish that goal.