ZHCS779B March   2012  – December 2023 UCC28070A

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Voltage Biasing (VCC and VVREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio and Sense Resistor (RS))
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Programmable Peak Current Limit

The UCC28070A has been designed with a programmable cycle-by-cycle peak current limit dedicated to disabling either the GDA or GDB output whenever the corresponding current-sense input (CSA or CSB, respectively) rises above the voltage established on the PKLMT pin. Once an output has been disabled through the detection of peak current limit, the output remains disabled until the next clock cycle initiates a new PWM period. The programming range of the PKLMT voltage extends to upwards of 4V to permit the full use of the 3V average current sense signal range; however, note that the linearity of the current amplifiers begins to compress above 3.6V.

A resistor-divider network from VREF to GND can easily program the peak current limit voltage on PKLMT, provided the total current out of VREF is less than 2mA to avoid drooping of the 6V VREF voltage. TI recommends a load of less than 0.5mA, but if the resistance on PKLMT is very high, TI recommends a small filter capacitor on PKLMT to avoid operational problems in high-noise environments.

GUID-7AD6002B-12F2-41D5-8365-DA137194D05B-low.gif Figure 6-3 Externally Programmable Peak Current Limit

Peak Current Limit is a protection feature and has no built-in slope-compensation for duty-cycles greater than 0.5. During occurrences of peak limiting, sub-harmonic oscillation will occur with possible audible noise from such oscillation. If the PKLMT feature is re-purposed to implement a steady-state power-limit function, suitable slope compensation should be added by external means.