ZHCS779B March   2012  – December 2023 UCC28070A

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
    1. 4.1 Pin Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Interleaving
      2. 6.3.2  Programming the PWM Frequency and Maximum Duty-Cycle Clamp
      3. 6.3.3  Frequency Dithering (Magnitude and Rate)
      4. 6.3.4  External Clock Synchronization
      5. 6.3.5  Multi-phase Operation
      6. 6.3.6  VSENSE and VINAC Resistor Configuration
      7. 6.3.7  VSENSE and VINAC Open-Circuit Protection
      8. 6.3.8  Current Synthesizer
      9. 6.3.9  Programmable Peak Current Limit
      10. 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
      11. 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
      12. 6.3.12 Voltage Biasing (VCC and VVREF)
      13. 6.3.13 PFC Enable and Disable
      14. 6.3.14 Adaptive Soft Start
      15. 6.3.15 PFC Start-Up Hold Off
      16. 6.3.16 Output Overvoltage Protection (OVP)
      17. 6.3.17 Zero-Power Detection
      18. 6.3.18 Thermal Shutdown
      19. 6.3.19 Current Loop Compensation
      20. 6.3.20 Voltage Loop Compensation
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Current Calculation
        2. 7.2.2.2 Bridge Rectifier
        3. 7.2.2.3 PFC Inductor (L1 and L2)
        4. 7.2.2.4 PFC MOSFETs (M1 and M2)
        5. 7.2.2.5 PFC Diode
        6. 7.2.2.6 PFC Output Capacitor
        7. 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio and Sense Resistor (RS))
        8. 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Trademarks
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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Current Loop Compensation

The UCC28070A incorporates two identical and independent transconductance-type current-error amplifiers (one for each phase) with which to control the shaping of the PFC input current waveform. The current-error amplifier (CA) forms the heart of the embedded current control loop of the boost PFC preregulator, and is compensated for loop stability using familiar principles [7, 8]. The output of the CA for phase-A is CAOA, and that for phase-B is CAOB. Because the design considerations are the same for both, they are collectively referred to as CAOx, where x is A or B.

In a boost PFC preregulator, the current control loop comprises the boost power plant stage, the current sensing circuitry, the wave-shape reference, the PWM stage, and the CA with compensation components. The CA compares the average boost inductor current sensed with the wave-shape reference from the multiplier stage and generates an output current proportional to the difference.

This CA output current flows through the impedance of the compensation network generating an output voltage, VCAO, which is then compared with a periodic voltage ramp to generate the PWM signal necessary to achieve PFC.

GUID-3B16726F-4661-4535-AC2A-79853AA50C98-low.gif Figure 6-5 Current Error Amplifier With Type II Compensation

For frequencies above boost LC resonance and below fPWM, the small-signal model of the boost stage, which includes current sensing, can be simplified to:

Equation 23. GUID-238CD3E7-6562-43CF-85B3-3F57B2BF64CF-low.gif

where:

  • LB = mid-value boost inductance
  • RS = CT sense resistor
  • NCT = CT turns ratio
  • VOUT = average output voltage of the PFC converter
  • ∆VRMP = 4Vpk-pk amplitude of the PWM voltage ramp
  • kSYNC = ramp reduction factor due to external synchronization frequency: kSYNC = (15000 / RRT(kΩ)) / fSYNC, where RRT(kΩ) is from Equation 8. When external synchronization is not used, kSYNC = 1.
  • s = Laplace complex variable

An RZC-CZC network is introduced on CAOx to obtain high gain for the low-frequency content of the inductor current signal, but reduced flat gain above the zero frequency out to fPWM to attenuate the high-frequency switching ripple content of the signal (thus averaging it).

The switching ripple voltage must be attenuated to less than 1/10 of the ΔVRMP amplitude so as to be considered negligible ripple.

Thus, CAOx gain at fPWM is:

Equation 24. GUID-0A32CAD8-405C-434C-9929-8E255A01480B-low.gif

where:

  • ∆ILB is the maximum peak-to-peak ripple current in the boost inductor
  • gmc is the transconductance of the CA, 100μS
Equation 25. R Z C   4 V   ×   N C T   ×   k S Y N C 10   ×   100 μ S   ×   I L B   ×   R S

The current-loop cross-over frequency is then found by equating the open loop gain to 1 and solving for fCXO:

Equation 26. GUID-C7D0D34C-A2F5-4604-BBA9-370DE099B916-low.gif

CZC is then determined by setting fZC = fCXO = 1 / (2π × RZC × CZC) and solving for CZC. At fZC = fCXO, a phase margin of 45° is obtained at fCXO. Greater phase margin may be had by placing fZC < fCXO.

An additional high-frequency pole is generally added at fPWM to further attenuate ripple and noise at fPWM and higher. This is done by adding a small-value capacitor, CPC, across the RZCCZCnetwork.

Equation 27. GUID-8D86BEB8-186C-4CA0-B176-D4E3C7A0C646-low.gif

The procedure above is valid for fixed-value inductors.

Note:

If a "swinging-choke" boost inductor (inductance decreases gradually with increasing current) is used, fCXO varies with inductance, so CZC must be determined at maximum inductance.