ZHCS779B March 2012 – December 2023 UCC28070A
PRODUCTION DATA
The UCC28070A contains two independent circuits dedicated to disabling the GDx outputs based on the biasing conditions of the VSENSE or SS pins. The first is a PFC Enable which monitors VVSENSE and holds off soft start and the overall PFC function until the output has precharged to approximately 25%. Before VVSENSE reaching 0.75V, almost all of the internal circuitry is disabled. Once VVSENSE reaches 0.75V and VVAO < 0.75V, the oscillator, multiplier, and current synthesizer are enabled and the SS circuitry begins to ramp up the voltage on the SS pin. The second circuit provides an external interface to emulate an internal fault condition to disable the GDx output without fully disabling the voltage loop and multiplier. By externally pulling the SS pin below 0.6V, the GDx outputs are immediately disabled and held low. Assuming no other fault conditions are present, normal PWM operation resumes when the external SS pulldown is released. The external pulldown must be sized large enough to override the internal 1.5mA adaptive SS pullup once the SS voltage falls below the disable threshold. TI recommends using a MOSFET with less than 100Ω RDS(on) resistance to ensure the SS pin is held adequately below the disable threshold.