SLVSIN8 June   2026 TPSM65660

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Internal LDO, VCC UVLO, and BIAS Input
      3. 7.3.3  Precision Enable and Adjustable Input Voltage UVLO (EN/UVLO)
      4. 7.3.4  Output Voltage Setpoint (FB, BIAS)
      5. 7.3.5  Adjustable Switching Frequency (RT)
      6. 7.3.6  Mode Selection and Clock Synchronization (MODE/SYNC)
        1. 7.3.6.1 Clock Synchronization
        2. 7.3.6.2 Clock Locking
      7. 7.3.7  Device Configuration (CNFG/SYNCOUT)
      8. 7.3.8  Dual Random Spread Spectrum (DRSS)
      9. 7.3.9  High-Side MOSFET Gate Drive (BST)
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Protection Features
        1. 7.3.11.1 Power-Good Monitor
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup-Mode Protection
        4. 7.3.11.4 Thermal Shutdown
      12. 7.3.12 Two-Phase, Single-Output Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Powertrain Components
        1. 8.1.1.1 Output Capacitors
        2. 8.1.1.2 Input Capacitors
        3. 8.1.1.3 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – 5V, 6A Synchronous Buck Regulator With Wide Input Voltage Range
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Choosing the Switching Frequency
          2. 8.2.1.2.2 Input Capacitor Selection
          3. 8.2.1.2.3 Output Capacitors
          4. 8.2.1.2.4 Output Voltage Setpoint
          5. 8.2.1.2.5 Compensation Components
          6. 8.2.1.2.6 Setting the Input Voltage UVLO
          7. 8.2.1.2.7 EMI Mitigation, RDRSS
          8. 8.2.1.2.8 Input Capacitor Selection
        3. 8.2.1.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

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机械数据 (封装 | 引脚)
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7.3.10 Soft Start and Recovery From Dropout

The TPSM656x0 module has a soft-start feature that slowly ramps the target regulation voltage to gradually reach the steady-state operating point, thus preventing output voltage overshoot and high inrush current at the input during start-up. The device initiates soft start based on any of these conditions:

  • Power applied to the VIN pins of the module, releasing UVLO for both VIN and VCC
  • EN/UVLO goes high, turning on the device
  • Recovery from a hiccup-waiting period
  • Recovery from thermal shutdown protection.

The simplest way to use the TPSM656x0 is to leave the SS pin open for a fixed soft-start time of 5.3ms. In applications with high output capacitance, high output voltage, or other special requirements, extend the soft-start time with a capacitor from SS to PGND. Use Equation 6 or refer to Figure 7-7 to select a value for CSS based on a desired soft-start time, tSS.

Equation 6. C S S [ n F ] = 16.7 × t S S [ m s ]

For example, for a desired soft-start time of 12ms, Equation 6 gives a value for CSS of 200nF. Select 220nF as the closest standard value.

TPSM65660 Setting the Soft-Start Time Figure 7-7 Setting the Soft-Start Time

Upon initiating soft start, the device takes the following actions:

  • The internal reference to regulate the output voltage slowly ramps from zero. The net result is that the output voltage takes tSS to reach 90% of the desired value.
  • The operating mode sets to AUTO, activating diode emulation such that a prebiased start-up occurs without pulling down on the output voltage.
  • Hiccup-mode protection remains disabled for the duration of soft start; see Section 7.3.11.3.

Together, these actions provide a start-up profile with limited inrush current and allow high output capacitance and high loading conditions such that the device can approach current limit during start-up without triggering hiccup. See Figure 7-8.

TPSM65660 Output Voltage Soft Start: No Prebias (a), With Prebias (b)
After soft start initiates, the output voltage reaches 90% of the output setpoint after a time interval, tSS. The device disables FPWM and hiccup during the soft-start interval, and subsequently enables these modes after the output voltage reaches regulation.
Figure 7-8 Output Voltage Soft Start: No Prebias (a), With Prebias (b)