SLVSIN8 June   2026 TPSM65660

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Internal LDO, VCC UVLO, and BIAS Input
      3. 7.3.3  Precision Enable and Adjustable Input Voltage UVLO (EN/UVLO)
      4. 7.3.4  Output Voltage Setpoint (FB, BIAS)
      5. 7.3.5  Adjustable Switching Frequency (RT)
      6. 7.3.6  Mode Selection and Clock Synchronization (MODE/SYNC)
        1. 7.3.6.1 Clock Synchronization
        2. 7.3.6.2 Clock Locking
      7. 7.3.7  Device Configuration (CNFG/SYNCOUT)
      8. 7.3.8  Dual Random Spread Spectrum (DRSS)
      9. 7.3.9  High-Side MOSFET Gate Drive (BST)
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Protection Features
        1. 7.3.11.1 Power-Good Monitor
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup-Mode Protection
        4. 7.3.11.4 Thermal Shutdown
      12. 7.3.12 Two-Phase, Single-Output Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Powertrain Components
        1. 8.1.1.1 Output Capacitors
        2. 8.1.1.2 Input Capacitors
        3. 8.1.1.3 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – 5V, 6A Synchronous Buck Regulator With Wide Input Voltage Range
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Choosing the Switching Frequency
          2. 8.2.1.2.2 Input Capacitor Selection
          3. 8.2.1.2.3 Output Capacitors
          4. 8.2.1.2.4 Output Voltage Setpoint
          5. 8.2.1.2.5 Compensation Components
          6. 8.2.1.2.6 Setting the Input Voltage UVLO
          7. 8.2.1.2.7 EMI Mitigation, RDRSS
          8. 8.2.1.2.8 Input Capacitor Selection
        3. 8.2.1.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
  • VCL|31
散热焊盘机械数据 (封装 | 引脚)

5 Pin Configuration and Functions

Figure 5-1 VCL 31-Pin QFN-FCMOD Package (Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
VIN11PInput supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this pin to the nearby GND pins 3 and 4. Provide a low-impedance connection to the VIN pin 24.
NC 2 — No connect pin. Leave floating to maintain 0.7mm clearance between VIN and GND pins. This pin can be shorted to GND provided the 0.4mm clearance between VIN and GND pins meets system pin clearance requirements.
GND 3, 4 G Power ground to the internal low-side MOSFET. Connect this pin to the system ground.
NC 5 — No connect pin. Leave floating.
BIAS 6 P Input to an internal voltage regulator. If configured for fixed VOUT, connect the pin to the VOUT node to close the control loop. If configured for an adjustable VOUT, connect the pin to the VOUT node or an external bias supply from 3.3V to 30V. If output voltage is above 30V and no external supply is used, tie the pin to GND.
DRSS/MCOMM 7 I/O Dual Random Spread-Spectrum (DRSS) select pin. See Dual Random Spread Spectrum (DRSS) for available DRSS options. If configured for dual-phase operation, this pin becomes a mode communication pin between a primary and a secondary device. For dual-phase operation, tie together the MCOMM pins of the primary and secondary devices.
VCC 8 P Internal regulator output. Used as supply to internal control circuits. Do not connect this pin to any external loads. Connect a high-quality 1µF capacitor from this pin to PGND.
PG9I/OPower-Good output pin. This pin is an open-drain output that goes low if the output voltage is outside of the specified regulation window.
COMP10AExternal compensation pin. This pin is the output of the transconductance amplifier. If used, connect a compensation network from the COMP pin to GND. If unused, tie the pin to either GND or VCC.
FB11AFeedback pin. Connect to GND to configure 3.3V fixed output voltage. Connect to VCC to configure 5V fixed output voltage. Connect this pin to a feedback divider tap point for adjustable output options. The regulation threshold is 0.8V.
VOUT 12, 13, 14 P Output voltage pins. The pins are connected to the internal output inductor. Connect the pins to the output load with a low impedance connection and connect external output capacitors between the pins and the system GND.
SS 15 A Soft-start delay programming pin. If the SS pin is left open, the internal soft-start circuit ramps the FB reference from zero to full value in 5.3ms. If a capacitor is connected from the SS pin to GND, the soft-start time can be set to a higher value.
GND16GGND pin. Connect to the system ground.
CNFG / SYNCOUT17I/OConfiguration pin. This pin configures the device as a primary (single-phase or dual-phase operation) or a secondary (dual-phase operation) and selects internal (single-phase operation) or external compensation (single-phase or dual-phase operation). If configured as a primary for dual-phase operation, the pin becomes a SYNCOUT pin after start-up.
MODE / SYNC18I/OMode and synchronization input pin. Tie this pin to GND or drive the pin low to operate in AUTO mode. Tie this pin to VCC or drive the pin high, or send a synchronization clock signal to operate in FPWM mode. When synchronized to an external clock, use the RT pin to set the internal frequency close to the synchronized frequency to avoid disturbances if the external clock is turned on and off.
RT19I/OSwitching frequency programming pin. Connect this pin to GND through a resistor with a value between 6.81kΩ and 54.2kΩ to set the switching frequency between 300kHz and 2200kHz. Connect to VCC for 400kHz operation. Connect to GND for 2.2MHz operation. Do not float.
EN / UVLO20I/OPrecision enable pin. Drive this pin high / low to enable / disable the device. This pin can be directly connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. Do not float.
NC21I/ONo connect pin. Leave floating.
GND22, 23GPower ground to the internal low-side MOSFET. Connect this pin to the system ground.
NC24—No connect pin. Leave floating to maintain 0.7mm clearance between GND and VIN2 pins. This pin can be shorted to GND provided the 0.4mm clearance between GND and VIN2 pins meet system pin clearance requirements.
VIN225PInput supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this pin to the nearby GND pins 22 and 23. Provide a low-impedance connection to the VIN pin 1.
SW26PPower module switch node. Intended for test purposes only. Leave floating.
BST27PBootstrap pin for the internal high-side driver upper supply rail. Intended for test purposes only. An integrated 100nF capacitor is connected between the SW node and BST pins. Leave floating.
GND28, 29, 30, 31GExposed GND pads. Connect to system GND on a PCB. These pads are a major heat dissipation path for the die. Use the pads for heat sinking by soldering to a large copper area on the PCB. Implementing as many thermal vias as suggested in the example board layout ensures the lowest package thermal resistance and best possible thermal performance.
(1) I/O = input / output, A = analog, G = ground, P = power