ZHCS447C SEPTEMBER   2011  – April  2018 TPS84210

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化应用
      2.      效率与输出电流间的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Package Specifications
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Switching Characteristics
    6. 6.6 Typical Characteristics (VIN = 5 V)
    7. 6.7 Typical Characteristics (VIN = 3.3 V)
  7. Functional Block Diagram
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting The Output Voltage
  9. Capacitor Recommendations For The TPS84210 Power Supply
    1. 9.1 Capacitor Technologies
      1. 9.1.1 Electrolytic, Polymer-Electrolytic Capacitors
      2. 9.1.2 Ceramic Capacitors
      3. 9.1.3 Tantalum, Polymer-Tantalum Capacitors
    2. 9.2 Input Capacitor
    3. 9.3 Output Capacitor
  10. 10Transient Response
  11. 11Application Schematics
  12. 12Power Good (PWRGD)
  13. 13Power-Up Characteristics
  14. 14Remote Sense
  15. 15Output On/Off Inhibit (INH)
  16. 16Slow Start (SS/TR)
  17. 17Overcurrent Protection
  18. 18Synchronization (CLK)
  19. 19Sequencing (SS/TR)
  20. 20Programmable Undervoltage Lockout (UVLO)
  21. 21Thermal Shutdown
  22. 22Layout Guidelines
  23. 23Layout Example
  24. 24EMI
  25. 25器件和文档支持
    1. 25.1 接收文档更新通知
    2. 25.2 社区资源
    3. 25.3 商标
    4. 25.4 静电放电警告
    5. 25.5 术语表
  26. 26机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 34, shows a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • Place ceramic input and output capacitors close to the module pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Place a dedicated AGND copper area beneath the TPS84210.
  • Connect the AGND and PGND copper area at one point; directly at the pin 37 PowerPad using multiple vias.
  • Place RSET, RRT, and CSS as close as possible to their respective pins.
  • Use multiple vias to connect the power planes to internal layers.