22.214.171.124 Device Reset Scenarios
The device has three reset scenarios:
- Full reset: All digital logic of device is reset.
- Caused by POR (power on reset) when VCC7 < VBNPR and BB < VBNPR
- General reset: No impact on the RTC, backup registers, or interrupt status.
- Caused by PWON_LP_RST bit set high
- Or DEV_OFF_RST bit set high
- Or HDRST input set high
- Turnoff: Power reinitialization in off/backup mode.
A mapping of digital registers to these reset scenarios is described in Table 6-6.