ZHCSI09S June 2010 – August 2018 TPS65911
The TPS65911 device is an integrated power management IC (PMIC) available in a 98-pin 0.65-mm pitch BGA package. It is designed for applications powered by powered by one Li-Ion or Li-Ion polymer battery cell, 3-series Ni-MH cells, or a 5-V input supply. It provides three step-down converters, one step-down controller with external FETs to support high current rails, eight LDOs, nine GPIOs, and EERPOM-programmable power sequencing to support a variety of processors and system sequencing requirements.
Two of the step-down converters, VDD1 and VDD2, provide power for processor cores and support dynamic voltage scaling using I2C interface. VDD1 and VDD2 have an output voltage range of 0.6 V to 3.3V. The converters have a 12.5-mV step size from 0.6 V to 1.5 V, and a VGAIN_SEL option to multiply this voltage by 2 or 3, with 3.3 V maximum output voltage. The third converter, VIO, provides power for I/O and memory. VIO has four selectable voltage outputs, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
The device includes 8 general-purpose LDOs with an output voltage range from 1 V to 3.3 V. Three of the LDOs (LDO1, LDO2, and LDO4) support 50-mV output voltage steps, and the remaining five LDOs (LDO3, LDO5, LDO6, LDO7, and LDO8) support 100-mV output voltage steps. The LDO voltages and other configuration are controlled by the I2C interface.
The power-up and power-down sequences are controlled by the embedded power controller and is pre-programmed using EEPROM. The power-up and power-down sequences assign each output rail to a sequence slot, and the delay time between slots is either 0.5 ms or 2 ms.
The device offers nine GPIOs. Four of the GPIOs (GPIO0, GPIO2, GPIO6, and GPIO7) can be configured to enable external resources, and can be included in the power sequences. The device also includes dedicated input and reset pins used to enable and disable the PMIC including PWRON, PWRHOLD, HDRST, and PWRDN. The NRESPWRON pin is a dedicated power-on reset output for a processor powered by the PMIC.